M16C5LD Datasheet, PDF (21/85 Pages) Renesas Technology Corp – RENESAS MCU

M16C/5LD Group, M16C/56D Group
2. Central Processing Unit (CPU)
2.1.8.6 Overflow Flag (O Flag)
The O flag becomes set to 1 when an arithmetic operation results in an overflow; otherwise it becomes
0.
2.1.8.7 Interrupt Enable Flag (I Flag)
The I flag enables maskable interrupts.
Maskable interrupts are disabled when the I flag is 0, and enabled when it is 1. The I flag is 0 when an
interrupt request is acknowledged.
2.1.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is 0. USP is selected when the U flag is 1.
The U flag becomes 0 when a hardware interrupt request is acknowledged or the INT instruction of
software interrupt number 0 to 31 is executed.
2.1.8.9 Processor Interrupt Priority Level (IPL)
IPL is a 3-bit register and assigns processor interrupt priority levels from 0 to 7.
If a requested interrupt has a higher priority than IPL, the interrupt is enabled.
2.1.8.10 Reserved Areas
Only write 0 to bits assigned as reserved areas. The read value is undefined.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
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