TL16C752C Datasheet, PDF (6/50 Pages) Texas Instruments – DUAL UART WITH 64-BYTE FIFO

TL16C752C
DUAL UART
WITH 64-BYTE FIFO
SLLS646 – MARCH 2008
www.ti.com
A. The vote logic determines whether the RX data is a logic 1 or 0. It takes three samples of the RX line and uses a
majority vote to determine the logic level received. The Vote logic operates on all bits received.
FUNCTIONAL DESCRIPTION
The TL16C752C UART is pin compatible with the TL16C2550 UART in the PFB package. It provides more
enhanced features. All additional features are provided through a special enhanced feature register.
The UART performs serial-to-parallel conversion on data characters received from peripheral devices or modems
and parallel-to-parallel conversion on data characters transmitted by the processor. The complete status of each
channel of the TL16C752C UART can be read at any time during functional operation by the processor.
The TL16C752C UART can be placed in an alternate mode (FIFO mode) relieving the processor of excessive
software overhead by buffering received/transmitted characters. Both the receiver and transmitter FIFOs can
store up to 64 bytes (including three additional bits of error status per byte for the receiver FIFO) and have
selectable or programmable trigger levels. Primary outputs RXRDY and TXRDY allow Signaling of DMA
transfers.
The TL16C752C UART has selectable hardware flow control and software flow control. Both schemes
significantly reduce software overhead and increase system efficiency by automatically controlling serial data
flow. Hardware flow control uses the RTS output and CTS input signals. Software flow control uses
programmable Xon/Xoff characters.
The TL16C752C includes a programmable baud rate generator that can divide the timing reference clock by a
divisor between 1 and 65535. A bit (MCR7) can be used to invoke a pre-scaler (divide by 4) off the reference
clock, prior to the baud rate generator input. The divide by 4 pre-scaler is selected when MCR7 is set to 1.
Trigger Levels
The TL16C752C UART provides independent selectable and programmable trigger levels for both receiver and
transmitter DMA and interrupt generation. After reset, both transmitter and receiver FIFOs are disabled and so, in
effect, the trigger level is the default value of one byte. The selectable trigger levels are available via the FCR.
The programmable trigger levels are available via the TLR.
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