TL16C752C Datasheet, PDF (41/50 Pages) Texas Instruments – DUAL UART WITH 64-BYTE FIFO

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TL16C752C
DUAL UART
WITH 64-BYTE FIFO
SLLS646 – MARCH 2008
Figure 30. IrDA-SIR Decoding Scheme – Detailed Timing
Diagram
Figure 31. IrDA-SIR Decoding Scheme – Macro View
It is possible for jitter or slight frequency differences to cause the next falling edge on Rx to be missed for one
16XCLK cycle. In that case, a 1-clock-wide pulse appears on Int_Rx between consecutive zeroes. It is important
for the UART to strobe Int_Rx in the middle of the bit time to avoid latching this 1-clock-wide pulse. The
TL16C550C UART already strobes incoming serial data at the proper time. Otherwise, note that data is required
to be framed by a leading zero and a trailing one. The falling edge of that first zero on Int_Rx synchronizes the
read strobe. The strobe occurs on the eighth 16XCLK pulse after the Int_Rx falling edge and once every 16
cycles thereafter until the stop bit occurs.
Figure 32. Timing Causing 1-Clock-Wide Pulse Between Consecutive Ones
Figure 33. Recommended Strobing for Decoded Data
Copyright © 2008, Texas Instruments Incorporated
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