TL16C752C Datasheet, PDF (35/50 Pages) Texas Instruments – DUAL UART WITH 64-BYTE FIFO

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TL16C752C
DUAL UART
WITH 64-BYTE FIFO
SLLS646 – MARCH 2008
Interrupt Identification Register (IIR)
The IIR is a read-only 8-bit register which provides the source of the interrupt in a prioritized manner. Table 15
shows interrupt identification register bit settings.
Table 15. Interrupt Identification Register (IIR) Bit
Settings
BIT NO.
0
3:1
4
5
7:6
BIT SETTINGS
0 = An interrupt is pending
1 = No interrupt is pending
3-Bit encoded interrupt. See Table 14.
1 = Xoff/Special character has been detected.
CTS/RTS low to high change of state
Mirror the contents of FCR[0]
The interrupt priority list is illustrated in Table 16.
PRIORITY
LEVEL
1
2
2
3
4
5
6
BIT 5
0
0
0
0
0
0
1
BIT 4
0
0
0
0
0
1
0
BIT 3
0
1
0
0
1
0
0
Table 16. Interrupt Priority List
BIT 2
1
1
1
0
0
0
0
BIT 1
1
0
0
1
0
0
0
BIT 0
0
0
0
0
0
0
0
INTERRUPT SOURCE
Receiver line status error
Receiver timeout interrupt
RHR interrupt
THR interrupt
Modem interrupt
Received Xoff signal/special character
CTS, RTS change of state from active (low) to inactive (high)
Enhanced Feature Register (EFR)
This 8-bit register enables or disables the enhanced features of the UART. Table 17 shows the enhanced feature
register bit settings.
BIT NO.
3:0
4
5
6
7
Table 17. Enhanced Feature Register (EFR) Bit Settings
BIT SETTINGS
Combinations of software flow control can be selected by programming bit 3−bit 0. See Table 1.
Enhanced functions enable bit.
0 = Disables enhanced functions and writing to IER[7:4], FCR[5:4], MCR[7:5].
1 = Enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5] can be modified, i.e., this bit is therefore a write
enable.
0 = Normal operation
1 = Special character detect. Received data is compared with Xoff-2 data. If a match occurs, the received data is
transferred to FIFO and IIR[4] is set to 1 to indicate a special character has been detected.
RTS flow control enable bit
0 = Normal operation
1 = RTS flow control is enabled i.e., RTS pin goes high when the receiver FIFO HALT trigger level TCR[3:0] is reached,
and goes low when the receiver FIFO RESTORE transmission trigger level TCR[7:4] is reached.
CTS flow control enable bit
0 = Normal operation
1 = CTS flow control is enabled i.e., transmission is halted when a high signal is detected on the CTS pin.
Copyright © 2008, Texas Instruments Incorporated
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