TL16C752C Datasheet, PDF (12/50 Pages) Texas Instruments – DUAL UART WITH 64-BYTE FIFO

TL16C752C
DUAL UART
WITH 64-BYTE FIFO
SLLS646 – MARCH 2008
www.ti.com
IIR[5–0]
000001
000110
001100
000100
PRIORITY
LEVEL
None
1
2
2
000010
3
000000
4
010000
5
100000
6
Table 4. Interrupt Control Functions
INTERRUPT
TYPE
None
Receiver line
status
RX timeout
RHR interrupt
THR interrupt
Modem status
Xoff interrupt
CTS, RTS
INTERRUPT SOURCE
INTERRUPT RESET METHOD
None
None
OE, FE, PE, or BI errors occur in
characters in the RX FIFO
FE < PE < BI: All erroneous characters are
read from the RX FIFO. OE: Read LSR
Stale data in RX FIFO
Read RHR
DRDY (data ready)
Read RHR
(FIFO disable)
RX FIFO above trigger level (FIFO enable)
TFE (THR empty)
(FIFO disable)
TX FIFO passes above trigger level (FIFO
enable)
Read IIR or a write to the THR
MSR[3:0]= 0
Read MSR
Receive Xoff character(s)/special character Receive Xon character(s)/Read of IIR
RTS pin or CTS pin change state from
active (low) to inactive (high)
Read IIR
It is important to note that for the framing error, parity error, and break conditions, LSR[7] generates the interrupt.
LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared only when there are no more errors
remaining in the FIFO. LSR[4–2] always represent the error status for the received character at the top of the Rx
FIFO. Reading the Rx FIFO updates LSR[4–2] to the appropriate status for the new character at the top of the
FIFO. If the Rx FIFO is empty, then LSR[4–2] is all zeros.
For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt is cleared by an Xon
flow character detection. If a special character detection caused the interrupt, the interrupt is cleared by a read of
the ISR.
Interrupt Mode Operation
In interrupt mode (if any bit of IER[3:0] is1), the processor is informed of the status of the receiver and transmitter
by an interrupt signal, INT. Therefore, it is not necessary to continuously poll the line status register (LSR) to see
if any interrupt needs to be serviced. Figure 5 shows interrupt mode operation.
Figure 5. Interrupt Mode Operation
Polled Mode Operation
In polled mode (IER[3:0] = 0000), the status of the receiver and transmitter can then be checked by polling the
line status register (LSR). This mode is an alternative to the interrupt mode of operation where the status of the
receiver and transmitter is automatically known by means of interrupts sent to the CPU. Figure 6 shows polled
mode operation.
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