TL16C752C Datasheet, PDF (3/50 Pages) Texas Instruments – DUAL UART WITH 64-BYTE FIFO

www.ti.com
NAME
A0
A1
A2
TERMINAL
NO.
PFB
RHB
28
18
27
17
26
16
CDA, CDB,
40, 16
CSA, CSB,
10, 11
7, 8
CTSA, CTSB,
38, 23 25, 15
D0–D4,
D5–D7
44–48,
1–3
27–31
32, 1, 2
DSRA, DSRB, 39, 20
DTRA, DTRB,
34, 35
22, 23
GND
INTA, INTB,
17
12
30, 29 20, 19
IOR
IOW
NC
OPA, OPB
19
13
15
11
12, 24
35, 37
32, 9
RESET
RIA, RIB,
36
24
41, 21
TERMINAL FUNCTIONS
TL16C752C
DUAL UART
WITH 64-BYTE FIFO
SLLS646 – MARCH 2008
I/O DESCRIPTION
I
Address bit 0 select. Internal registers address selection. Refer to Table 7 for Register
Address Map.
I
Address bit 1 select. Internal registers address selection. Refer to Table 7 for Register
Address Map.
I
Address bit 2 select. Internal registers address selection. Refer to Table 7 for Register
Address Map.
Carrier detect (active low). These inputs are associated with individual UART channels A
I through B. A low on these pins indicates that a carrier has been detected by the modem
for that channel.
Chip select A and B (active low). These pins enable data transfers between the user
I CPU and the TL16C752C for the channel(s) addressed. Individual UART sections (A, B,
C, D) are addressed by providing a low on the respective CSA through CSD pin.
Clear to send (active low). These inputs are associated with individual UART channels A
and B. A low on the CTS pins indicates the modem or data set is ready to accept
I transmit data from the TL16C752C. Status can be checked by reading MSR[4]. These
pins only affect the transmit and receive operations when auto CTS function is enabled
through the enhanced feature register (EFR[7]), for hardware flow control operation.
Data bus (bidirectional). These pins are the eight-bit, 3-state data bus for transferring
I/O information to or from the controlling CPU. D0 is the least significant bit and the first data
bit in a transmit or receive serial data stream.
Data set ready (active low). These inputs are associated with individual UART channels
I A through B. A low on these pins indicates the modem or data set is powered on and is
ready for data exchange with the UART.
Data terminal ready (active low). These outputs are associated with individual UART
channels A through B. A low on these pins indicates that the TL16C752C is powered on
O
and ready. These pins can be controlled through the modem control register. Writing a 1
to MCR[0] sets the DTR output to low, enabling the modem. The output of these pins is
high after writing a 0 to MCR[0], or after a reset. These pins can also be used in the
RS-485 mode to control an external RS-485 driver or transceiver.
Pwr Power signal and power ground
Interrupt A and B (active high). These pins provide individual channel interrupts, INTA-D.
INTA−D are enabled when MCR[3] is set to a 1, interrupts are enabled in the interrupt
O enable register (IER) and when an interrupt condition exists. Interrupt conditions include:
receiver errors, available receiver buffer data, transmit buffer empty, or when a modem
status flag is detected. INTA−D are in the high-impedance state after reset.
Read input (active low strobe). A valid low level on IOR loads the contents of an internal
I register defined by address bits A0–A2 onto the TL16C752C data bus (D0–D7) for
access by an external CPU.
Write input (active low strobe). A valid low level on IOW transfers the contents of the
I data bus (D0–D7) from the external CPU to an internal register that is defined by
address bits A0–A2.
No internal connection
User defined outputs. This function is associated with individual channels A and B. The
state of these pins is defined by the user through the software settings of the MCR
O
register, bit 3. INTA-B are set to active mode and OP to a logic 0 when the MCR-3 is set
to a logic 1. INTA-B are set to the 3-state mode and OP to a logic 1 when MCR-3 is set
to a logic 0. See bit 3, modem control register (MCR bit 3). The output of these two pins
is high after reset.
Reset. RESET resets the internal registers and all the outputs. The UART transmitter
I output and the receiver input are disabled during reset time. See TL16C752C external
reset conditions for initialization details. RESET is an active high input.
Ring indicator (active low). These inputs are associated with individual UART channels A
and B. A logic low on these pins indicates the modem has received a ringing signal from
I the telephone line. A low-to-high transition on these input pins generates a modem
status interrupt, if enabled. The state of these inputs is reflected in the modem status
register (MSR).
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TL16C752C
Submit Documentation Feedback
3