TL16C752C Datasheet, PDF (11/50 Pages) Texas Instruments – DUAL UART WITH 64-BYTE FIFO

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TL16C752C
DUAL UART
WITH 64-BYTE FIFO
SLLS646 – MARCH 2008
Table 2. Register Reset Functions⁽¹⁾
REGISTER
Interrupt enable register
Interrupt identification register
FIFO control register
Line control register
Modem control register
Line status register
Modem status register
Enhanced feature register
Receiver holding register
Transmitter holding register
Transmission control register
Trigger level register
Alternate function register
RESET
CONTROL
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET STATE
All bits cleared
Bit 0 is set. All other bits cleared.
All bits cleared
Reset to 00011101 (1D hex).
All bits cleared
Bits 5 and 6 set. All other bits cleared.
Bits 0–3 cleared. Bits 4–7 input signals.
All bits cleared
Pointer logic cleared
Pointer logic cleared
All bits cleared
All bits cleared
All bits (except AFR4) cleared; AFR4 set
(1) Registers DLL, DLH, SPR, Xon1, Xon2, Xoff1, Xoff2 are not reset by the top-level reset signal RESET,
i.e., they hold their initialization values during reset.
Table 3 summarizes the state of outputs after reset.
Table 3. Signal Reset Functions
SIGNAL
TX
RTS
DTR
RXRDYA–B
TXRDYA–B
RESET CONTROL
RESET
RESET
RESET
RESET
RESET
RESET STATE
High
High
High
High
Low
Interrupts
The TL16C752C UART has interrupt generation and prioritization (six prioritized levels of interrupts) capability.
The interrupt enable register (IER) enables each of the six types of interrupts and the INT signal in response to
an interrupt generation. The IER also can disable the interrupt system by clearing bits 0−3, 5−7. When an
interrupt is generated, the interrupt identification register(IIR) indicates that an interrupt is pending and provides
the type of interrupt through IIR[5−0]. Table 4 summarizes the interrupt control functions.
Copyright © 2008, Texas Instruments Incorporated
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