TL16C752C Datasheet, PDF (23/50 Pages) Texas Instruments – DUAL UART WITH 64-BYTE FIFO

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TL16C752C
DUAL UART
WITH 64-BYTE FIFO
SLLS646 – MARCH 2008
TIMING REQUIREMENTS
T_A = 0°C to 70°C, V_CC = 1.8 V to 5 V ±10% (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
t_{RES Reset pulse width}
ET
C_P CP Clock period
t_3w Oscillator/Clock speed
t_6s Address setup time
t_6h Address hold time
t_7w IOR strobe width
t_9d Read cycle delay
t_12d Delay from IOR to data
t_12h Data disable time
t_13w IOW strobe width
t_15d Write cycle delay
t_16s Data setup time
t_16h Data hold time
t_17d Delay from IOW to output
t_18d
Delay to set interrupt from
MODEM input
See Figure 15 and Figure 16
See Figure 15 and Figure 16
See Figure 16
See Figure 16
See Figure 15
See Figure 15
See Figure 15
See Figure 15
50 pF load, See Figure 17
50 pF load, See Figure 17
t_19d
Delay to reset interrupt from
IOR
50 pF load
t_20d Delay from stop to set interrupt See Figure 18
t_21d
Delay from IOR to reset
interrupt
50 pF load, See Figure 18
t_22d Delay from stop to interrupt
t_23d
Delay from initial IOW reset to
transmit star
See Figure 21
See Figure 21
t_24d
Delay from IOW to reset
interrupt
See Figure 21
t_25d Delay from stop to set RXRDY See Figure 19 and Figure 20
t_26d Delay from IOR to reset RXRDY See Figure 19 and Figure 20
t_27d Delay from IOW to set TXRDY See Figure 22 and Figure 23
t_28d Delay from start to reset TXRDY See Figure 22 and Figure 23
1.8 V
MIN MAX
200
63
16
20
15
85
85
65
35
85
85
40
35
60
70
80
1
55
1
8 24
75
1
1
70
16
LIMITS
2.5 V
3.3 V
MIN MAX MIN MAX
200
200
42
32
24
32
15
10
10
7
70
50
70
60
50
35
25
20
70
50
70
60
30
20
25
15
40
30
55
45
55
1
45
1
8 24
40
1
35
1
8 24
45
35
1
1
1
1
60
50
16
16
5V
MIN MAX
200
20
48
5
5
40
50
25
15
40
50
15
10
20
35
30
1
25
1
8 24
25
1
1
40
16
UNIT
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Baudrate
ns
Baudrate
Baudrate
ns
Baudrate
µs
ns
Baudrate
Copyright © 2008, Texas Instruments Incorporated
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