TL16C752C Datasheet, PDF (30/50 Pages) Texas Instruments – DUAL UART WITH 64-BYTE FIFO

TL16C752C
DUAL UART
WITH 64-BYTE FIFO
SLLS646 – MARCH 2008
www.ti.com
Table 8. TL16C752C Internal Registers⁽¹⁾⁽²⁾
SPECIAL
CONSIDERATIONS
ADDR
000
000
001
LCR[7] = 0
010
010
None
011
100
LCR[7:0] ≠
101
1011 1111
110
111
000
LCR[7] = 1
001
LCR[7:5] = 100
010
010
100
LCR[7:0] =
1011 1111
101
110
111
110
EFR[4] = 1 and
MCR[6] = 1
111
MCR[4] = 0 and
MCR[2] = 1
111
REGISTER BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RHR
THR
IER
FCR
IIR
LCR
MCR
LSR
MSR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit1
CTS
interrupt
enable
RTS
interrupt
enable
Xoff
interrupt
enable
Sleep
mode
Modem
status
interrupt
Rx line
status
interrupt
THR
empty
interrupt
Rx trigger Rx trigger TX trigger TX trigger
level
level
level
level
DMA
mode
select
Resets Resets Rx
Tx FIFO FIFO
FCR(0)
Interrupt Interrupt Interrupt
FCR(0) CTS, RTS
Xoff
priority Bit priority priority Bit
2
Bit 1
0
DLAB and
EFR
enable
Break
control bit
Sets parity
Parity type
select
Parity
enable
No. of
stop bits
Word
length
1× or 4×
clock
TCR and
TLR enable
Xon any
Enable
loopback
IRQ FIFORdy
enable Enable
RTS
Error in Rx THR and
FIFO TSR empty
THR
empty
Break
interrupt
Framing
error
Parity
error
Overrun
error
CD
RI
DSR
CTS
ΔCD
ΔRI
ΔDSR
bit 0
bit 0
Rx data
available
interrupt
Enables
FIFOs
Interrupt
status
Word
length
DTR
Data in
receiver
ΔCTS
SPR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit1
bit 0
DLL
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit1
bit 0
DLH
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
AFR
EFR
Xon1
DLY2
Auto-CTS
bit 7
DLY1
Auto-RTS
bit 6
DLY0
RCVEN 485LG 485RN
IREN
CONC
Special Enable S/W flow S/W flow S/W flow S/W flow
character enhanced- control Bit control control Bit control Bit
detect functions
3
Bit 2
1
0
bit 5
bit 4
bit 3
bit 2
bit1
bit 0
Xon2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit1
bit 0
Xoff1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit1
bit 0
Xoff2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit1
bit 0
TCR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit1
bit 0
TLR
FIFORdy
bit 7
RX FIFO
D status
bit 6
RX FIFO
C status
bit 5
RX FIFO
B status
bit 4
RX FIFO
A status
bit 3
bit 2
bit1
TX FIFO TX FIFO TX FIFO
D status C status B status
bit 0
TX FIFO
A status
READ/
WRITE
Read
Write
Read/
write
Write
Read
Read/
write
Read/
write
Read
Read
Read/
write
Read/
write
Read/
write
Read/
write
Read/
write
Read/
write
Read/
write
Read/
write
Read/
write
Read/
write
Read/
write
Read
(1) Bits represented by shaded cells can only be modified if EFR[4] is enabled, i.e., if enhanced functions are enabled.
(2) Refer to the notes under Table 7 for more register access information.
Receiver Holding Register (RHR)
The receiver section consists of the receiver holding register (RHR) and the receiver shift register (RSR). The
RHR is actually a 64-byte FIFO. The RSR receives serial data from RX terminal. The data is converted to parallel
data and moved to the RHR. The receiver section is controlled by the line control register. If the FIFO is disabled,
location zero of the FIFO is used to store the characters. If overflow occurs, characters are lost. The RHR also
stores the error status bits associated with each character.
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