HD404019R Datasheet, PDF (59/65 Pages) Renesas Technology Corp – CMOS 4-bit single-chip microcomputers

HD404019R Series
Serial Interface Timing Characteristics
(HD404019R: V_CC = 3.5 V to 6 V, GND = 0 V, V_disp = V_CC – 40 V to V_CC, Ta = –20°C to +75°C
HD40L4019R: V_CC = 2.7 V to 6 V, GND = 0 V, V_disp = V_CC – 40 V to V_CC, Ta = –20°C to +75°C
HD4074019: V_CC = 4.5 V to 5.5 V, GND = 0 V, V_disp = V_CC – 40 V to V_CC, Ta = –20°C to +75°C
HD407L4019: V_CC = 3.0 V to 5.5 V, GND = 0 V, V_disp = V_CC – 40 V to V_CC, Ta = –20°C to +75°C
unless otherwise specified)
Item
Symbol Pin
Min Typ Max Unit Test Conditions
Notes
Transmit clock t_Scyc
cycle time
SCK output 1
— — t_cyc Load shown in figure 30
1, 2
Transmit clock t_SCKH
SCK output 0.4 —
—
t _cyc
1, 2
high widths
Transmit clock t_SCKL
SCK output 0.4 —
—
t _cyc
1, 2
low widths
Transmit clock t_SCKr
rise time
SCK output — — 40 ns HD404019R, HD4074019, 1, 2
HD407L4019
— — 40 ns HD40L4019R:
1, 2
V_CC = 3.5 V to 6.0 V
— — 200 ns HD40L4019R
1, 2
Transmit clock t_SCKf
fall time
SCK output — — 40 ns HD404019R, HD4074019, 1, 2
HD407L4019
— — 40 ns HD40L4019R:
1, 2
V_CC = 3.5 V to 6.0 V
— — 200 ns HD40L4019R
1, 2
Transmit clock t_Scyc
SCK input 1
—
—
t _cyc
1
cycle time
Transmit clock t_SCKH
SCK input 0.4 —
—
t _cyc
1
high width
Transmit clock t_SCKL
SCK input 0.4 —
—
t _cyc
1
low width
Transmit clock t_SCKHD
SCK input 1
—
—
t _cyc
3
completion
detect time
Transmit clock t_SCKr
SCK input — — 40 ns
1
rise time
Transmit clock t_SCKf
SCK input — — 40 ns
1
fall time
Notes: 1. See figure 29.
2. See figure 30.
3. Transmit clock completion detect time is the high level period after 8 pulses of transmit clock are
input. The serial interrupt request flag is not set when the next transmit clock is input before the
transmit clock completion detect time has passed.
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