HD404019R Datasheet, PDF (22/65 Pages) Renesas Technology Corp – CMOS 4-bit single-chip microcomputers

HD404019R Series
The contents of the serial mode register will be changed on the second instruction cycle after the serial
mode register has been written to. Therefore, the STS instruction must be executed after the data in the
serial mode register has been changed completely. The serial mode register will be reset to $0 by MCU
reset.
Table 7
SMR3
0
1
Serial Mode Register
R4₀/SCK
Used as R4₀ port input/output pin
Used as SCK input/output pin
SMR2
0
1
SMR1
0
1
0
1
SMR0
0
1
0
1
0
1
0
1
Transmit Clock
R4₀/SCK Port
SCK output
SCK output
SCK output
SCK output
SCK output
SCK output
SCK output
SCK input
Clock Source
Prescaler
Prescaler
Prescaler
Prescaler
Prescaler
Prescaler
System clock
External clock
Prescaler Divide System Clock
Ratio
Divide Ratio
÷ 2048
÷ 4096
÷ 512
÷ 1024
÷ 128
÷ 256
÷ 32
÷ 64
÷8
÷ 16
÷2
÷4
—
÷1
—
—
Serial Data Register (SRL: $006, SRU: $007): The 8-bit read/write serial data register consists of a low-
order digit (SRL: $006) and a high-order digit (SRU: $007).
The data in the serial data register is output from the SO pin, from LSB to MSB, synchronously with the
falling edge of the transmit clock signal. At the same time, external data is input from the SI pin to the
serial data register, MSB first, synchronously with the rising edge of the transmit clock. Figure 10 shows
the I/O timing chart of the transmit clock signal and the data.
The read/write operations of the serial data register should be performed after the completion of data
transmit/receive. Otherwise the data may not be guaranteed.
Transmit clock
Serial output data
Serial input data
latch timing
12 345 678
LSB
MSB
Figure 10 Serial Interface I/O Timing
20