HD404019R Datasheet, PDF (26/65 Pages) Renesas Technology Corp – CMOS 4-bit single-chip microcomputers

HD404019R Series
Timers
The MCU contains a prescaler and two timer/counters (timers A and B). See figure 13. The prescaler is an
11-bit binary counter, timer A an 8-bit free-running timer, and timer B is an 8-bit auto-reload timer/event
counter.
INT₁
System
clock
Timer mode register B
TMB (4 bits)
3
Timer B MPX
CPTB
Prescaler (11 bits)
Internal bus line (S1)
4
TL (4 bits)
4
Timer latch register
TCB (8 bits)
Timer counter B
TLR (8 bits)
Timer load register B
TBOF
IFTB
Interrupt
request flag
of timer B
4
4
Internal bus line (S2)
Timer A MPX
3
TMA (3 bits)
CPTA
TCA (8 bits)
Timer counter A
TAOF
IFTA
Interrupt
request flag
of timer A
Timer mode register A
Figure 13 Timer/Counter Block Diagram
Prescaler: The input to the prescaler is the system clock signal. The prescaler is initialized to $0000 by
MCU reset, and it starts to count up with the system clock signal as soon as RESET input goes to logic 0.
The prescaler keeps counting up except at MCU reset and stop mode. The prescaler provides clock signals
to timer A, timer B, and the serial interface. The prescaler divide ratio is selected by timer mode register A
(TMA), timer mode register B (TMB), or the serial mode register (SMR).
Timer A Operation: After timer A is initialized to $00 by MCU reset, it counts up at every clock input
signal. When the next clock signal is applied after timer A becomes $FF, it generates an overflow and
becomes $00. This overflow causes the timer A interrupt request flag (IFTA: $001, bit 2) to go to 1. This
timer can function as an interval timer periodically generating overflow output at every 256th clock signal
input.
The clock input signals to timer A are selected by timer mode register A (TMA: $008).
Timer B Operation: Timer mode register B (TMB: $009) selects the auto-reload function, input clock
source, and the prescaler divide ratio of timer B. When the external event input is used as an input clock
signal to timer B, select R3₃/INT₁ as INT₁ and set the external interrupt mask (IM1) to prevent an external
interrupt request from occurring.
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