HD404019R Datasheet, PDF (24/65 Pages) Renesas Technology Corp – CMOS 4-bit single-chip microcomputers

HD404019R Series
In the transmit clock wait state the falling edge of the first transmit clock causes the serial interface to shift
to the transfer state. The octal counter then counts up and the serial data register shifts simultaneously. As
an exception, if the clock continuous output mode is selected, the serial interface stays in the transmit clock
wait state while the transmit clock outputs continuously.
The octal counter becomes 000 again after 8 transmit clocks or the execution of the STS instruction, so the
serial interface returns to the transmit clock wait state and the serial interrupt request flag is set
simultaneously.
When the internal transmit clock is selected, the transmit clock output is triggered by the execution of the
STS instruction, and stops after 8 clocks.
Change PMR^*
Write to SMR
STS waiting state
octal counter = 000
transmit clock disable
STS
instruction
Write to
SMR
(IFS ← 1)
Change PMR^*
Transmit clock wait state
(octal counter = 000)
Transmit clock
8 transmit clocks,
STS instruction
(IFS ← 1)
Transfer state
(octal counter ≠ 000)
Note: * Change PMR means the operation mode changes as shown below.
Clock
continuous
output mode
• Transmit mode
• Receive mode
• Transmit/receive mode
Figure 11 Serial Interface Operation State
Transmit Clock Error Detection Example: The serial interface functions abnormally when the transmit
clock is disturbed by external noise. Transmit clock errors can be detected by the procedure shown in figure
12.
If more than 8 transmit clocks occur in the transfer state, the state of the serial interface shifts as follows:
transfer state, transmit clock wait state, and transfer state. The serial interrupt flag should be reset before
entering into the STS state by writing data to SMR. This procedure sets the IFS again.
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