HD404019R Datasheet, PDF (12/65 Pages) Renesas Technology Corp – CMOS 4-bit single-chip microcomputers

HD404019R Series
Bit 3
0
IM0
(IM of INT₀)
1
IMTA
(IM of timer A)
2
Not used
3
Not used
Bit 2
IF0
(IF of INT₀)
IFTA
(IF of timer A)
Not used
Not used
Bit 1
RSP
(Reset SP bit)
IM1
(IM of INT₁)
IMTB
(IM of timer B)
IMS
(IM of serial)
Bit 0
IE
(Interrupt enable flag)
$000
IF1
(IF of INT₁)
IFTB
(IF of timer B)
$001
$002
IFS
(IF of serial)
$003
IF: Interrupt request flag
IM: Interrupt mask
IE: Interrupt enable flag
SP: Stack pointer
Note: Each bit of the interrupt control bit area is set by the SEM/SEMD instruction, reset by the
REM/REMD instruction, and tested by the TM/TMD instruction. It is not affected by other
instructions. Furthermore the interrupt request flag is not affected by the SEM/SEMD
instruction. The value of the status flag becomes invalid when the unusable bits are tested.
Figure 3 Interrupt Control Bits Area Configuration
Memory registers
Stack area
32 MR (0) $020 960 Level 16 $3C0
33 MR (1) $021
34 MR (2) $022
35 MR (3) $023
36 MR (4) $024
Level 15
Level 14
Level 13
Level 12
37 MR (5) $025
Level 11
38 MR (6) $026
Level 10
39 MR (7) $027
Level 9
40 MR (8) $028
Level 8
41 MR (9) $029
Level 7
42 MR (10) $02A
Level 6
43 MR (11) $02B
Level 5
44 MR (12) $02C
Level 4
45 MR (13) $02D
Level 3
46 MR (14) $02E
Level 2
47 MR (15) $02F 1023 Level 1 $3FF
PC₁₃ to PC₀: Program counter
ST: Status flag
CA: Carry flag
Bit 3
1020 ST
1021 PC₁₀
1022 CA
1023 PC₃
Bit 2
PC₁₃
PC₉
PC₆
PC₂
Bit 1
PC₁₂
PC₈
PC₅
PC₁
Bit 0
PC₁₁ $3FC
PC₇ $3FD
PC₄ $3FE
PC₀ $3FF
Figure 4 Configuration of Memory Registers, Stack Area, and Stack Position
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