HD404019R Datasheet, PDF (16/65 Pages) Renesas Technology Corp – CMOS 4-bit single-chip microcomputers

HD404019R Series
Figure 7 shows the interrupt processing sequence, and figure 8 shows the interrupt processing flowchart. If
an interrupt is requested, the instruction being executed finishes in the first cycle. The IE is reset in the
second cycle. In the second and third cycles, the carry flag, status flag, and program counter are pushed
onto the stack. In the third cycle, the instruction is re-executed after jumping to the vector address.
At each vector address, program the JMPL instruction to branch to the starting address of the interrupt
program. The IF which caused the interrupt must be reset by software in the interrupt program.
$000,0
IE
$000,2
IF0
$000,3
IM0
$001,0
IF1
$001,1
IM1
$001,2
IFTA
$001,3
IMTA
$002,0
IFTB
$002,1
IMTB
$003,0
IFS
$003,1
IMS
Sequence control
• Push PC/CA/ST
• Reset IE
• Jump to vector address
Priority control
logic
Vector
address
Note: $m, n is RAM address $m, bit number n.
Figure 6 Interrupt Control Circuit Block Diagram
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