HD404019R Datasheet, PDF (29/65 Pages) Renesas Technology Corp – CMOS 4-bit single-chip microcomputers

HD404019R Series
The counter value of timer B can be obtained by reading timer counter B. In this case, read the high-order
digit first, and then the low-order digit. The count value of the low-order digit is latched at the time when
the high-order digit is read.
Timer A Interrupt Request Flag (IFTA: $001, Bit 2): The timer A interrupt request flag is set by the
overflow output of timer A (table 13).
Table 13 Timer A Interrupt Request Flag
IFTA
0
1
Interrupt Request
No
Yes
Timer A Interrupt Mask (IMTA: $001, Bit 3): The timer A interrupt mask prevents an interrupt request
from being generated by the timer A interrupt request flag (table 14).
Table 14 Timer A Interrupt Mask
IMTA
0
1
Interrupt Request
Enabled
Disabled (masked)
Timer B Interrupt Request Flag (IFTB: $002, Bit 0): The timer B interrupt request flag is set by the
overflow output of timer B (table 15).
Table 15 Timer B Interrupt Request Flag
IFTB
0
1
Interrupt Request
No
Yes
Timer B Interrupt Mask (IMTB: $002, Bit 1): The timer B interrupt mask prevents an interrupt request
from being generated by the timer B interrupt request flag (table 16).
Table 16 Timer B Interrupt Mask
IMTB
0
1
Interrupt Request
Enabled
Disabled (masked)
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