M16C6NL Datasheet, PDF (383/388 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

REVISION HISTORY
M16C/6N Group (M16C/6NL, M16C/6NN) Hardware Manual
Rev. Date
2.00 Nov. 28, 2005
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Description
Summary
Figure 8.9 Examples of Main Clock Connection Circuit is revised.
Figure 8.10 Examples of Sub Clock Connection Circuit is revised.
8.1.4 PLL Clock
• 9th line: The sentence (When the PLL ... to) is added.
8.2.1 CPU Clock and BCLK
• 10th line: The sentence (During memory expansion ...) is added.
8.4.1.6 On-chip Oscillator Mode: Last sentence (When the operation mode is ...) is added.
8.1.1.7 On-chip Oscillator Low Power Dissipation Mode: Last sentence (When the
operation mode is ...) is deleted.
Table 8.4 Pin Status During Wait Mode is revised.
Table 8.6 Interrrupts to Stop Mode and Use Conditions is added.
Table 8.7 Pin Status in Stop Mode is revised.
Figure 8.13 State Transition in Normal Operation Mode: NOTE 7 is deleted.
Figure 10.4 Interrupt Control Registers (2): NOTE 2 is added.
10.5.8 Returning from an Interrupt Routine: Las sentence (Register bank ...) is added.
10.5.9 Interrupt Priority: First sentence (If two or more...) is revised.
10.5.10 Interrupt Priority Resolution Circuit: First sentence (The interrupt priority level ...)
is revised.
Figure 10.12 IFSR1 Register: NOTES 2 and 4 are revised.
10.10 Address Match Interrupt
• Second line from the bottom: sentence (Note that when ...) is added.
Table 12.1 DMAC Specifications: DMA transfer Cycles is added.
12.1 Transfer Cycle: 3rd and 4th sentences (During ... /Furthermore ...) are revised.
12.1.2 Effect of BYTE Pin Level is added.
12.1.3 Effect of Software Wait: 3rd to 9th lines is moved from next section of 12.1.2.
________
12.1.4 Effect of RDY Signal is added.
Table 12.2 DMA Transfer Cycles is revised.
Table 12.3 Coefficient j, k is revised.
12.5 Channel Priority and DMA Transfer Timing: Last sentence (Refer to ...) is added.
Figure 13.12 TA0MR to TA4MR Registers in PWM Mode: b2 is revised from “1” to “(blank)”.
Figure 14.1 Three-Phase Motor Control Timer Function Block Diagram is revised.
Figure 14.2 UNVC0 Register: NOTES 5 and 6 are revised.
Figure 15.5 U0BRG to U2BRG Registers (lower): NOTE 3 is added.
Figure 15.6 U0C0 to U2C0 Registers (lower): NOTE 5 is added.
Table 15.9 Example of Bit Rates and Settings: 20 MHz is added.
Figure 15.37 SiC Register (upper): NOTE 7 is added.
Figure 15.37 SiBRG Register (middle): NOTE 4 is added.
Figure 16.1 A/D Converter Block Diagram
• ADGSEL1 to ADGSEL0 (righit/lower) is revised from “10b” to “11b”.
• NOTE 1 is added.
16.2.6 Output Impedance of Sensor under A/D Conversion
• 10th line: f(XIN) is revised to f(φAD).
Figure 16.10 Analog Input Pin and External Sensor Equivalent Circuit
• fAD is revised to φAD.
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