M16C6NL Datasheet, PDF (244/388 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NL, M16C/6NN)
19. CAN Module
CAN0 Configuration Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
C0CONR
Address
021Ah
After Reset
Indeterminate
Bit Symbol
Bit Name
Function
RW
b3 b2 b1 b0
0 0 0 0 : Divide-by-1 of fCAN
BRP
Prescaler Division
Ratio Select Bits
0 0 0 1 : Divide-by-2 of fCAN
0 0 1 0 : Divide-by-3 of fCAN
RW
1 1 1 0 : Divide-by-15 of fCAN
1 1 1 1 : Divide-by-16 of fCAN ⁽¹⁾
Sampling Control 0 : One time sampling
SAM _Bit
1 : Three times sampling
RW
b7 b6 b5
0 0 0 : 1Tq
Propagation Time 0 0 1 : 2Tq
PTS Segment Control ^{0 1 0 : 2Tq}
RW
Bits
1 1 0 : 7Tq
1 1 1 : 8Tq
NOTE:
1. fCAN serves for the CAN clock. The period is decided by configuration of the CCLKi bit (i = 0 to 2) in the CCLKR register.
(b15)
(b8)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
C0CONR
Address
021Bh
After Reset
Indeterminate
Bit Symbol
Bit Name
Function
RW
b2 b1b0
0 0 0 : Do not set a value
Phase Buffer
0 0 1 : 2Tq
PBS1 Segment 1
0 1 0 : 3Tq
RW
Control Bits
1 1 0 : 7Tq
1 1 1 : 8Tq
b5 b4 b3
0 0 0 : Do not set a value
Phase Buffer
0 0 1 : 2Tq
PBS2 Segment 2
0 1 0 : 3Tq
RW
Control Bits
1 1 0 : 7Tq
1 1 1 : 8Tq
b7 b6
Resynchronization 0 0 : 1Tq
SJW Jump Width
0 1 : 2Tq
RW
Control Bits
1 0 : 3Tq
1 1 : 4Tq
Figure 19.11 C0CONR Register
Rev.2.00 Nov 28, 2005 page 228 of 364
REJ09B0126-0200