M16C6NL Datasheet, PDF (107/388 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NL, M16C/6NN)
10. Interrupt
Interrupt Request Cause Select Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR1
Address
01DFh
After Reset
00h
Bit Symbol
Bit Name
Function
RW
IFSR10
INT0 Interrupt Polarity
Switching Bit
0 : One edge
1 : Both edges ⁽¹⁾
RW
IFSR11
INT1 Interrupt Polarity
Switching Bit
0 : One edge
1 : Both edges ⁽¹⁾
RW
IFSR12
INT2 Interrupt Polarity
Switching Bit
0 : One edge
1 : Both edges ⁽¹⁾
RW
IFSR13
INT3 Interrupt Polarity
Switching Bit
0 : One edge
1 : Both edges ⁽¹⁾
RW
IFSR14
INT4 Interrupt Polarity
Switching Bit
0 : One edge
1 : Both edges ⁽¹⁾
RW
IFSR15
INT5 Interrupt Polarity
Switching Bit
0 : One edge
1 : Both edges ⁽¹⁾
RW
IFSR16
Interrupt Request Cause
Select Bit ⁽²⁾
0 : SI/O3 ⁽³⁾
1 : INT4
RW
IFSR17
Interrupt Request Cause
Select Bit ⁽⁴⁾
0 : SI/O4 ⁽⁵⁾
1 : INT5
RW
NOTES:
1.When setting this bit to "1" (both edges), make sure the POL bit in the INT0IC to INT5IC register is set
to "0" (falling edge).
2.SI/O3 and INT4 share the vector and interrupt control register. When using SI/O3 interrupt, set the
IFSR16 bit to "0" (SI/O3). When using INT4 interrupt, set the IFSR16 bit to "1" (INT4).
During memory expansion and microprocessor modes, when the data bus is 16-bit width (BYTE pin is
"L"), set this bit to "0" (SI/O3).
3.When setting this bit to "0" (SI/O3), make sure the IFSR00 bit in the IFSR0 register is set to "1" (SI/O3)
simultaneously. And, make sure the POL bit in the S3IC register is set to "0" (falling edge).
4.SI/O4 and INT5 share the vector and interrupt control register. When using SI/O4 interrupt, set the
IFSR17 bit to "0" (SI/O4). When using INT5 interrupt, set the IFSR17 bit to "1" (INT5).
During memory expansion and microprocessor modes, when the data bus is 16-bit width (BYTE pin is
"L"), set this bit to "0" (SI/O4).
5.When setting this bit to "0" (SI/O4), make sure the IFSR03 bit in the IFSR0 register is set to "1" (SI/O4)
simultaneously. And, make sure the POL bit in the S4IC register is set to "0" (falling edge).
Figure 10.12 IFSR1 Register
Rev.2.00 Nov 28, 2005 page 91 of 364
REJ09B0126-0200