M16C6NL Datasheet, PDF (211/388 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NL, M16C/6NN)
15.2.1 SI/Oi Operation Timing
Figure 15.39 shows the SI/Oi operation timing.
15. Serial Interface
"H"
SI/Oi internal clock _"L"
"H"
CLKi output _"L"
Signal written to the "H"
SiTRR register "L"
SOUTi output ^"H"
"L"
SINi input ^"H"
"L"
1.5 cycle (max.) ⁽¹⁾
D0
D1
D2
D3
D4
D5
D6
(NOTE 2)
D7
IR bit in SiIC register ^"1"
"0"
SiTRF bit in "1"
S3456TRR register "0"
i = 3 to 6 (5 and 6 are only in the 128-pin version.)
* This diagram applies to the case where the bits in the SiC register are set as follows:
SMi2 = 0 (SOUTi output)
SMi3 = 1 (SOUTi output, CLKi function)
SMi4 = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock)
SMi5 = 0 (LSB first)
SMi6 = 1 (internal clock)
NOTES:
1. If the SMi6 bit = 1 (internal clock), the serial I/O starts sending or receiving data a maximum of 1.5 transfer clock cycles after writing to the
SiTRR register.
2. When the SMi6 bit = 1 (internal clock), the SOUTi pin is placed in the high-impedance state after the transfer finishes.
Figure 15.39 SI/Oi Operation Timing
15.2.2 CLK Polarity Selection
The SMi4 bit in the SiC register allows selection of the polarity of the transfer clock.
Figure 15.40 shows the polarity of the transfer clock.
(1) When SMi4 bit in SiC register = 0
CLKi
(NOTE 1)
SOUTi
D0 D1 D2 D3 D4 D5 D6 D7
SINi
D0 D1 D2 D3 D4 D5 D6 D7
(2) When SMi4 bit in SiC register = 1
CLKi
(NOTE 2)
SOUTi
D0 D1 D2 D3 D4 D5 D6 D7
SINi
D0 D1 D2 D3 D4 D5 D6 D7
i = 3 to 6 (5 and 6 are only in the 128-pin version.)
*This diagram applies to the case where the bits in the SiC register are set as follows:
SMi5 = 0 (LSB first)
SMi6 = 1 (internal clock)
NOTES:
1. When the SMi6 bit = 1 (internal clock), a high level is output from the CLKi pin if not
transferring data.
2. When the SMi6 bit = 1 (internal clock), a low level is output from the CLKi pin if not
transferring data.
Figure 15.40 Polarity of Transfer Clock
Rev.2.00 Nov 28, 2005 page 195 of 364
REJ09B0126-0200