M16C5L_15 Datasheet, PDF (19/116 Pages) Renesas Technology Corp – RENESAS MCU

M16C/5L Group, M16C/56 Group
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. Seven registers (R0, R1, R2, R3, A0, A1, and FB) out of 13 compose a
register bank, and there are two register banks.
b31
R2
R3
b15
b8 b7
b0
R0H (upper bits of R0) R0L (lower bits of R0)
R1H (upper bits of R1) R1L (lower bits of R1)
R2
R3
A0
A1
FB
Data registers ⁽¹⁾
Address registers ⁽¹⁾
Frame base registers ⁽¹⁾
b19
b15
INTBH
INTBL
b0
Interrupt table register
INTBH is the 4 upper bits of the INTB register and INTBL
is the 16 lower bits.
b19
b0
PC
Program counter
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
Flag register
b15
IPL
b8 b7
b0
U I OB S Z DC
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Note:
1. These registers compose a register bank. There are two register banks.
Figure 2.1 CPU Registers
R01DS0035EJ0110 Rev.1.10
Sep 01, 2011
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