HYB18L256169BF Datasheet, PDF (8/48 Pages) Qimonda AG – 256-Mbit Mobile-RAM

HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
1. At first, device core power (V_DD) and device IO power (V_DDQ) must be brought up simultaneously. Typically V_DD
and V_DDQ are driven from a single power converter output.
Assert and hold CKE and DQM to a HIGH level.
2. After V_DD and V_DDQ are stable and CKE is HIGH, apply stable clocks.
3. Wait for 200µs while issuing NOP or DESELECT commands.
4. Issue a PRECHARGE ALL command, followed by NOP or DESELECT commands for at least t_RP period.
5. Issue two AUTO REFRESH commands, each followed by NOP or DESELECT commands for at least t_RC
period.
6. Issue two MODE REGISTER SET commands for programming the Mode Register and Extended Mode
Register, each followed by NOP or DESELECT commands for at least t_MRD period; the order in which both
registers are programmed is not important. Programming of the Extended Mode Register may be omitted when
default values (half drive strength, 4 bank refresh) will be used.
Following these steps, the Mobile-RAM is ready for normal operation.
2.2
Register Definition
2.2.1 Mode Register
The Mode Register is used to define the specific mode of operation of the Mobile-RAM. This definition includes
the selection of a burst length (bits A0-A2), a burst type (bit A3), a CAS latency (bits A4-A6), and a write burst
mode (bit A9). The Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and
BA1 = 0) and will retain the stored information until it is programmed again or the device loses power.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating any subsequent operation. Violating either of these requirements results in unspecified operation.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
MR
Mode Register Definition
(BA[1:0] = 00_B)
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
0
0
0
0
WB
0
0
CL
BT
BL
Field Bits Type Description
WB 9
w
Write Burst Mode
0 Burst Write
1 Single Write
CL [6:4] w
CAS Latency
010 2
011 3
Note: All other bit combinations are RESERVED.
BT 3
w
Burst Type
0 Sequential
1 Interleaved
Data Sheet
8
Rev. 1.02, 2006-12
02032006-MP0M-7FQG