HYB18L256169BF Datasheet, PDF (10/48 Pages) Qimonda AG – 256-Mbit Mobile-RAM

HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
5. Whenever a boundary of the block is reached within a given sequence, the following access wraps within the
block.
2.2.1.2 Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the
burst type and the starting column address, as shown in Table 5.
2.2.1.3 Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a READ command and
the availability of the first piece of output data. The latency can be programmed to 2 or 3 clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available with clock
edge n + m (for details please refer to the READ command description).
2.2.1.4 Write Burst Mode
When A9 = 0, the burst length programmed via A0-A2 applies to both read and write bursts; when A9 = 1, write
accesses consist of single data elements only.
2.2.1.5 Extended Mode Register
The Extended Mode Register controls additional low power features of the device. These include the Partial Array
Self Refresh (PASR, bits A0-A2)), the Temperature Compensated Self Refresh (TCSR, bits A3-A4)) and the drive
strength selection for the DQs (bits A5-A6). The Extended Mode Register is programmed via the MODE
REGISTER SET command (with BA0 = 0 and BA1 = 1) and will retain the stored information until it is programmed
again or the device loses power.
The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified
time before initiating any subsequent operation. Violating either of these requirements result in unspecified
operation.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
EMR
Extended Mode Register
BA1 BA0 A12 A11 A10 A9
1
0
0
0
0
0
(BA[1:0] = 10_B)
A8 A7 A6 A5
0
0
DS
A4 A3
(TCSR)
A2 A1 A0
PASR
Field Bits
DS [6:5]
TCSR [4:3]
Type Description
w
Selectable Drive Strength
00 Full Drive Strength
01 Half Drive Strength (default)
Note: All other bit combinations are RESERVED.
w
Temperature Compensated Self Refresh
XX Superseded by on-chip temperature sensor (see text)
Data Sheet
10
Rev. 1.02, 2006-12
02032006-MP0M-7FQG