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HYB18L256169BF Datasheet, PDF (16/48 Pages) Qimonda AG – 256-Mbit Mobile-RAM
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2.4.4 ACTIVE
#, +
#+ % (IG H
#3
2! 3
#! 3
7%
! ! 
2!
"! " !
"!
$O NgT# ARE
"!" AN K!D DRES S
2!  2 O W! DD RES S
Figure 9 ACTIVE Command
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
Before any READ or WRITE commands can be issued
to a bank within the Mobile-RAM, a row in that bank
must be “opened” (activated). This is accomplished via
the ACTIVE command and addresses A0 - A12, BA0
and BA1 (see Figure 9), which decode and select both
the bank and the row to be activated. After opening a
row (issuing an ACTIVE command), a READ or WRITE
command may be issued to that row, subject to the tRCD
specification. A subsequent ACTIVE command to a
different row in the same bank can only be issued after
the previous active row has been “closed”
(precharged).
The minimum time interval between successive
ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can
be issued while the first bank is being accessed, which
results in a reduction of total row-access overhead. The
minimum time interval between successive ACTIVE
commands to different banks is defined by tRRD.
#, +
#OM MA ND !# 4
! ! 2/ 7
"!  "!  "!X
./ 0
T22 $
Figure 10 Bank Activate Timings
!# 4
2/ 7
"!Y
./ 0
./ 0 2$ 7 2
./ 0
#/ ,
T2# $
"!Y
$O NgT#A RE
Table 9 Timing Parameters for ACTIVE Command
Parameter
Symbol
- 7.5
Units
min.
max.
ACTIVE to ACTIVE command period
tRC
67
–
ns
ACTIVE to READ or WRITE delay
tRCD
19
–
ns
ACTIVE bank A to ACTIVE bank B delay
tRRD
15
–
ns
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
Notes
1)
1)
1)
Data Sheet
16
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
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