HYB18L256169BF Datasheet, PDF (42/48 Pages) Qimonda AG – 256-Mbit Mobile-RAM

HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Electrical Characteristics
3.2
AC Characteristics
Table 20 AC Characteristics^1)2)3)4)
Parameter
Symbol
- 7.5
min.
max.
Clock cycle time
CL = 3
t_CK
7.5
—
CL = 2
9.5
—
Clock frequency
CL = 3
f_CK
—
133
CL = 2
—
105
Access time from CLK
CL = 3
t_AC
—
5.4
CL = 2
—
6.0
Clock high-level width
Clock low-level width
Address, data and command input setup time
Address and command input hold time
Data (DQ) input hold time
t_CH
2.5
—
t_CL
2.5
—
t_IS
1.5
—
t_IH
0.5
—
0.8
—
MODE REGISTER SET command period
t_MRD
2
—
DQ low-impedance time from CLK
t_LZ
1.0
–
DQ high-impedance time from CLK
t_HZ
3.0
7.0
Data out hold time
t_OH
2.5
—
DQM to DQ High-Z delay (READ Commands)
t_DQZ
—
2
DQM write mask latency
t_DQW
0
—
ACTIVE to ACTIVE command period
t_RC
67
—
ACTIVE to READ or WRITE delay
t_RCD
19
—
ACTIVE bank A to ACTIVE bank B delay
t_RRD
15
—
ACTIVE to PRECHARGE command period
t_RAS
45
100k
WRITE recovery time
t_WR
14
—
PRECHARGE command period
t_RP
19
—
Refresh period (8192 rows)
t_REF
—
64
Self refresh exit time
t_SREX
1
—
1) 0 °C ≤ T_C ≤ 70 °C (comm.); -25 °C ≤ T_C ≤ 85 °C (extended); V_DD = V_DDQ = 1.70V to 1.95V;
2) All parameters assumes proper device initialization.
3) AC timing tests measured at 0.9 V.
4) The transition time t_T is measured between V_IH and V_IL; all AC characteristics assume t_T = 1 ns.
5) Specified t_AC and t_OH parameters are measured with a 30 pF capacitive load only as shown below:
I/O
30 pF
Unit Notes
ns —
ns
MHz —
MHz
ns
5)6)
ns
ns —
ns —
ns
7)
ns
7)
t_CK
—
ns —
ns —
ns
5)6)
t_CK
—
t_CK
—
ns
8)
ns
8)
ns
8)
ns
8)
ns
9)
ns
8)
ms —
t_CK
—
6) If t_T(CLK) > 1 ns, a value of (t_T/2 - 0.5) ns has to be added to this parameter.
7) If t_T > 1 ns, a value of [0.5 x (t_T - 1)] ns has to be added to this parameter.
8) These parameter account for the number of clock cycles and depend on the operating frequency, as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
9) The write recovery time of t_WR = 14 ns allows the use of one clock cycle for the write recovery time when f_CK ≤ 72 MHz.
With f_CK > 72 MHz two clock cycles for t_WR are mandatory. Qimonda recommends to use two clock cycles for the write
recovery time in all applications.
Data Sheet
42
Rev. 1.02, 2006-12
02032006-MP0M-7FQG