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HYB18L256169BF Datasheet, PDF (18/48 Pages) Qimonda AG – 256-Mbit Mobile-RAM
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HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
Table 10 Timing Parameters for READ
Parameter
Symbol
- 7.5
Units
min.
max.
Access time from CLK
CL = 3
tAC
–
5.4
ns
CL = 2
tAC
–
6.0
ns
DQ low-impedance time from CLK
tLZ
1.0
–
ns
DQ high-impedance time from CLK
tHZ
3.0
7.0
ns
Data out hold time
tOH
2.5
–
ns
DQM to DQ High-Z delay (READ Commands)
tDQZ
–
2
tCK
ACTIVE to ACTIVE command period
tRC
67
–
ns
ACTIVE to READ or WRITE delay
tRCD
19
–
ns
ACTIVE to PRECHARGE command period
tRAS
45
100k
ns
PRECHARGE command period
tRP
19
–
ns
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
Notes
–
–
–
–
1)
1)
1)
1)
During READ bursts, the valid data-out element from the starting column address is available following the CAS
latency after the READ command. Each subsequent data-out element is valid nominally at the next positive clock
edge. Upon completion of a READ burst, assuming no other READ command has been initiated, the DQs go to
High-Z state.
Figure 13 and Figure 14 show single READ bursts for each supported CAS latency setting.
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Figure 13 Single READ Burst (CAS Latency = 2)
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Data Sheet
18
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
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