HYB18L256169BF Datasheet, PDF(13/48 Page) Qimonda AG – 256-Mbit Mobile-RAM

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HYB18L256169BF Datasheet, PDF (13/48 Pages) Qimonda AG – 256-Mbit Mobile-RAM

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HY[B/E]18L256169BF-7.5

256-Mbit Mobile-RAM

Functional Description

2.4

Commands

Table 6 Command Overview

Command

CS RAS CAS WE DQM Address Notes

NOP DESELECT

HX X X X

X

1)

NO OPERATION

LH HH X

X

1)

ACT ACTIVE (Select bank and row)

L L H H X Bank / Row 2)

RD READ (Select bank and column and start read burst) L H L H L/H Bank / Col 3)

WR WRITE (Select bank and column and start write burst) L H L L L/H Bank / Col 3)

BST BURST TERMINATE or

LH H L X

X

4)

DEEP POWER DOWN

PRE PRECHARGE (Deactivate row in bank or banks)

LL HL X

Code

5)

ARF AUTO REFRESH or

LL LH X

X

6)7)

SELF REFRESH (enter self refresh mode)

MRS MODE REGISTER SET

L L L L X Op-Code 8)

â

Data Write / Output Enable

ââ â â L

â

9)

â

Write Mask / Output Disable (High-Z)

ââ â â H

â

9)

1) DESELECT and NOP are functionally interchangeable.

2) BA0, BA1 provide bank address, and A0 - A12 provide row address.

3) BA0, BA1 provide bank address, A0 - A8 provide column address; A10 HIGH enables the Auto Precharge feature (non

persistent), A10 LOW disables the Auto Precharge feature.

4) This command is BURST TERMINATE if CKE is HIGH, DEEP POWER DOWN if CKE is LOW. The BURST TERMINATE

command is defined for READ or WRITE bursts with Auto Precharge disabled only.

5) A10 LOW: BA0, BA1 determine which bank is precharged.

A10 HIGH: all banks are precharged and BA0, BA1 are âDonât Careâ.

6) This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

7) Internal refresh counter controls row and bank addressing; all inputs and I/Os are âDonât Careâ except for CKE.

8) BA0, BA1 select either the Mode Register (BA0 = 0, BA1 = 0) or the Extended Mode Register (BA0 = 0, BA1 = 1); other

combinations of BA0, BA1 are reserved; A0 - A12 provide the op-code to be written to the selected mode register.

9) DQM LOW: data present on DQs is written to memory during write cycles; DQ output buffers are enabled during read

cycles;

DQM HIGH: data present on DQs are masked and thus not written to memory during write cycles; DQ output buffers are

placed in High-Z state (two clocks latency) during read cycles.

Address (A0 - A12, BA0, BA1), write data (DQ0 - DQ15) and command inputs (CKE, CS, RAS, CAS, WE, DQM)

are all registered on the positive edge of CLK. Figure 5 shows the basic timing parameters, which apply to all

commands and operations.

#,+

)N PUT

T#+

T#(

T#,

6A LID

T)3 T)(

6A LID

6A LID

Figure 5

! ! " !"! #3 # + %2 ! 3# ! 37 %

$O NgT#A RE

Address / Command Inputs Timing Parameters

Data Sheet

13

Rev. 1.02, 2006-12

02032006-MP0M-7FQG

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