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HYB18L256169BF Datasheet, PDF (36/48 Pages) Qimonda AG – 256-Mbit Mobile-RAM
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2.4.10 POWER DOWN
#, +
#+ %
#3
2! 3
#! 3
7%
! ! 
"! " !
$O NgT#A RE
Figure 45 Power Down Entry Command
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
Power-down is entered when CKE is registered LOW
(no accesses can be in progress). If power-down
occurs when all banks are idle, this mode is referred to
as precharge power-down; if power-down occurs when
there is a row active in any bank, this mode is referred
to as active power-down. Entering power-down
deactivates the input and output buffers, excluding CLK
and CKE. CKE LOW must be maintained during power-
down.
Power-down duration is limited by the refresh
requirements of the device (tREF).
The power-down state is synchronously exited when
CKE is registered HIGH (along with a NOP or
DESELECT command). One clock delay is required for
power down entry and exit.
#, +
#+ %
#O MM AND 02%
!DD RESS
!!0 0RE! LL
$1
T20
./ 0
./ 0
(IG H :
./ 0
6ALID
6ALID
6ALID
0OW ER$O WN
%N TRY
%X ITFRO M
!NY
0OWE R$O WN #O MMAN D
0RECHA RGE0OWE R$O WN MOD ESH OWN ALLBAN KSARE ID LE AND T20 MET
WHE N0OW E R$O WN % NTRY#O MMA NDISISS UED
$O NgT#A RE
Figure 46 Power Down Entry and Exit
2.4.10.1 DEEP POWER DOWN
The deep power down mode is an unique function on Low Power SDRAM devices with extremely low current
consumption. Deep power down mode is entered using the BURST TERMINATE command (cf. Figure 35) except
that CKE is LOW. All internal voltage generators inside the device are stopped and all memory data is lost in this
mode. To enter the deep power down mode all banks must be precharged.
The deep power down mode is asynchronously exited by asserting CKE HIGH. After the exit, the same command
sequence as for power-up initialization, including the 200µs initial pause, has to be applied before any other
command may be issued (cf. Figure 3 and Figure 4).
Data Sheet
36
Rev. 1.02, 2006-12
02032006-MP0M-7FQG
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