SAA1575HL Datasheet, PDF (9/56 Pages) NXP Semiconductors – Global Positioning System GPS baseband processor

Philips Semiconductors
Global Positioning System (GPS)
baseband processor
Product specification
SAA1575HL
SYMBOL PIN I/O
DESCRIPTION
V_CC(R)
72
− Backup core power supply: 2.4 to 3.6 V only. Separate from the core supply to allow
a low capacity battery to be used to maintain the Real-Time Clock (RTC) function.
This should be powered from the main supply during normal operation and switched
to battery backup when the main supply fails.
DMCS
73
O External data memory select: external RAM select pin, active LOW when the
external data memory space is addressed. This output is driven from V_CC(R) and
V_CC(B) supplies to ensure that the external RAM is not enabled during power-down.
PWRFAIL
74
I Power fail indicator: a LOW on this pin forces the embedded microcontroller into
reset. Reset will not be de-asserted until a set time after both PWRDN and PWRFAIL
go HIGH. For correct start-up, this pin should be LOW on power-up.
XTAL4
75
O Crystal 4: output from the RTC oscillator amplifier; this pin is only 3 V tolerant
XTAL3
76
I Crystal 3: input to inverting amplifier used in the RTC oscillator circuits (32.768 kHz);
this pin is only 3 V tolerant
PWRB
77
O Backup supply select: this output is intended to drive an external FET used to switch
the battery backup supply(s). It is active LOW and is controlled directly by the
PWRFAIL.
PWRM
78
O Main supply select: this output is intended to drive an external FET used to switch
the main supply(s). It is active LOW and is controlled directly by PWRFAIL.
V_SS
V_CC(B)
79
− Ground: 0 V reference
80
− Backup I/O power supply: 2.4 to 5.5 V only. Supply for the RAM select, power fail
and power switching I/O pads only allowing these functions to be powered when the
main power supply fails. This should be powered from the main supply during normal
operation and switched to battery backup when the main supply fails.
TXD1
81
O Transmitter output 1: transmit channel for serial port 1 (UART1) of the embedded
processor
RXD1
82
I Receiver input 1: receive channel for serial port 1 (UART1) of the embedded
processor. It is intended that this serial port is dedicated to differential GPS
information (dependent on firmware).
TXD0
83
O Transmitter output 0: transmit channel for serial port 0 (UART0) of the embedded
processor.
RXD0
84
I Receiver input 0: receive channel for serial port 0 (UART0) of the embedded
processor. It is intended that this serial port is dedicated to the NMEA data stream
(dependent on firmware).
V_SS
V_CC(P)
85
− Ground: 0 V reference
86
− Main I/O power supply: 2.7 to 5.5 V operating range; main supply for the periphery
in normal operation
GPIO4
87
I/O GPIO bit 4: standard general purpose I/O mapped into the segment 15 of the address
space. The top 4 bits can be used as the XA external timer control access pins
(T0, T1, T2 and T2EX).
GPIO3
88
I/O GPIO bit 3: standard general purpose I/O mapped into the segment 15 of the address
space. The top 4 bits can be used as the XA external timer control access pins
(T0, T1, T2 and T2EX).
RFDAT
89
O RFIC set-up data: serial data output used to set up the UAA1570HL front-end IC.
RFCLK
90
O RFIC set-up data: clock output for the serial data output used to set up the
UAA1570HL front-end IC. The state of the RFDAT and RFLE lines is latched into the
front-end IC on the rising edge.
1999 Jun 04
9