SAA1575HL Datasheet, PDF (23/56 Pages) NXP Semiconductors – Global Positioning System GPS baseband processor

Philips Semiconductors
Global Positioning System (GPS)
baseband processor
Product specification
SAA1575HL
7.8.2.3 Example of strategy for fast supplies
The second example will operate correctly in circuits
where the delay between the supplies to the peripheral
and core power domains is significant compared to the rise
times of the power supplies. This may occur in cases
where the core supply is a regulated (delayed) version of
the peripheral supply. If the previous strategy were used in
this situation, it would be possible for the SAA1575HL to
miss the PWRFAIL LOW state at power-up, resulting in the
IC not being given a correct reset.
In this example, the PWRDN logic input is derived as
before by comparing the V_CC(P) supply voltage against a
known reference voltage. But in this instance the
PWRFAIL logic input is derived by comparing the V_CC(core)
core supply against a threshold voltage.
As V_CC(P) falls, the first threshold level is reached and
PWRDN is taken LOW. This triggers an interrupt in the
firmware which is used to perform any required
housekeeping. At the end of the interrupt routine, the
firmware places the SAA1575HL into reset.
However, if the fall times on the supplies is fast, it is likely
that the PWRFAIL input will go LOW before the interrupt
routine has been completed. This would force the
SAA1575HL into immediate reset. At this time both PWRM
and PWRB toggle to switch backup supply sources.
On power-up, the V_CC(P) supply rises quickly. However,
since this only controls an interrupt flag and the
SAA1575HL is still held in reset by PWRFAIL, this has no
effect. Only once the V_CC(core) supply rises will PWRFAIL
be de-asserted. This can only occur once the V_CC(core)
voltage has reached the set threshold, and so there is no
risk of the IC ‘missing’ the reset pulse. The SAA1575HL
will come out of reset a set time after this, depending on
the state of the input pin RSTIME.
handbook, full pagewidth
VCC(P)
VCC(core)
PWRDN
PWRFAIL
PWRB
PWRM
Vt1
Vt3
delay while XA in
interrupt routine
reset timer delay
set by RSTIME
Fig.12 Example of power-down strategy with fast supplies.
MHB471
1999 Jun 04
23