SAA1575HL Datasheet, PDF (16/56 Pages) NXP Semiconductors – Global Positioning System GPS baseband processor

Philips Semiconductors
Global Positioning System (GPS)
baseband processor
Product specification
SAA1575HL
7.5 CPU peripheral features
The SAA1575HL contains the hardware for 3 timers,
2 UARTs, a watchdog timer, a 3-bit RF IC programming
link and an 8-bit general purpose I/O port.
7.5.1 TIMERS/COUNTERS
The SAA1575HL has 2 standard 16-bit timer/counters and
a third 16-bit up/down timer/counter. These timer/event
counters can perform the following functions:
• Measure time intervals and pulse duration
• Count external interrupts
• Generate interrupt requests
• Generate Pulse Width Modulation (PWM) or timed
output waveforms.
The timers are used by the standard Philips firmware to
generate the baud rates for the UART serial ports.
The additional features are not used in the standard
Philips firmware but are available for use in custom
firmware revisions.
All of the timers are configured in the 16-bit auto-reload
mode of operation. Timer 1 is used to generate the baud
rate for UART0 and Timer 2 is used to generate the baud
rate for UART1. In the standard Philips firmware, Timer 0
is not used.
7.5.2 WATCHDOG TIMER
The watchdog timer protects the system from incorrect
code execution by causing a processor reset if the
watchdog timer underflows as a result of a failure of the
firmware to feed the timer prior to it reaching its terminal
count.
In the standard Philips firmware, the watchdog is enabled
with a time-out period of 130 ms (at a clock frequency of
30 MHz).
With the standard Philips firmware, both UARTs are
configured to be in Mode 1: variable rate 8-bit operation.
Ten bits are transmitted (via TXDn) or received
(via RXDn): a START bit, 8 data bits (LSB first), and a
STOP bit.
In general, the UART clocks (which are 16 times the baud
rate) are determined by the Timer 1 or Timer 2 overflow
rate. With the standard Philips firmware, Timer 1 is used to
generate the baud rate for UART0 and Timer 2 is used to
generate the baud rate for UART1. The baud rate is set to
be 4800 bits/s for both UARTs.
7.5.4 RF IC PROGRAMMING PORT
The SAA1575HL is capable of programming the
UAA1570HL via a standard 3-wire serial link. This consists
of a clock line (SCLK), data line (D15 to D0) and a latch
enable (RFLE). Data is clocked into a holding register in
the UAA1570HL serially on each rising edge of the output
RFCLK. Once the complete serial packet has been
clocked into the RF IC, the latch enable output, RFLE, is
asserted which copies the new word from the holding
register in the RF IC into the control registers.
Proper timing of the clock, data and latch outputs is
ensured by firmware. An example sequence is illustrated
in Fig.7. The signals shown would result in the value 1001
being loaded into the last 4 bits of the RF IC serial register.
Each loading operation of the RF IC reloads the complete
RF control register.
With the standard Philips firmware, a 20-bit long word
0X5E320 is transmitted in this manner on start-up or
re-initialization. This gives full compatibility with the Philips
UAA1570HL front-end IC. See the “UAA1570HL” for more
details about the configuration options of the front-end IC.
7.5.3 UARTS
The SAA1575HL contains 2 UART ports, compatible with
the enhanced UART modes 1 to 3 on the 8xC51FB
(mode 0 operations not supported). With the exception of
the removal of the mode 0 operation, the UARTs in the
SAA1575HL are identical to those in the XA-G3 product.
Each UART rate is determined by either a fixed division of
the oscillator (in UART mode 2) or by one of the timer
overflow rates (in UART modes 1 and 3).
1999 Jun 04
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