SAA1575HL Datasheet, PDF (19/56 Pages) NXP Semiconductors – Global Positioning System GPS baseband processor

Philips Semiconductors
Global Positioning System (GPS)
baseband processor
Product specification
SAA1575HL
7.7 The external bus
The off-chip memories and the on-chip registers are on the
same address and data bus. The routing of the data and
address signals between the on-chip registers and the
off-chip memories is controlled by a block known as the
external bus interface. In addition, certain chip enable
signals are decoded within the block to reduce the amount
of external glue logic required in the complete system.
The address latch, normally required on 80C51 systems,
is implemented within the SAA1575HL. Therefore, no ALE
signal is seen outside the IC and address and data lines
are brought out on separate pins.
However, since internally there is still the need to latch the
address from a common address/data bus, signals on the
data bus will be seen to change during the address set-up
cycles.
The lower 3 external address lines are driven directly by
the XA core and are not latched. This allows ‘burst’ code
reads to be performed in which adjacent code locations
are accessed without the need for an address latch cycle.
Signals similar to those used by a standard 80C51 or XA
system are used to control the external bus activity.
handbook, full pagewidth
ALE
A4 to A19
D15 to D0
XA
A3 to A1
WRH, WRL, RD
PMCS
to MMRS
A1 to A8 D15 to D0 ENABLE
LE
ADDRESS
LATCH
16
ADDRESS
DECODER
DMCS
16
A4 to A19
16
D15 to D0
3
A3 to A1
3
WRH, WRL, RD
PMCS
MHB469
Fig.10 SAA1575HL internal address and data routing.
1999 Jun 04
19