SAA1575HL Datasheet, PDF (13/56 Pages) NXP Semiconductors – Global Positioning System GPS baseband processor

Philips Semiconductors
Global Positioning System (GPS)
baseband processor
Product specification
SAA1575HL
7.4 Memory organization
The memory space in the SAA1575HL is configured in a
Harvard architecture which means that the code and data
memory are organized in separate address spaces. This
section describes the SAA1575HL memory requirements.
7.4.1 DATA MEMORY SPACE
The SAA1575HL contains 2 kbytes words of internal data
memory. For correct firmware operation, a further
32 kbytes words of external data memory is needed with a
maximum access time of 100 ns.
The specifications of this external memory are firmware
dependent. The figures given in this document are for the
standard Philips firmware. With other revisions of firmware
the timings could differ by integer numbers of XTAL1 clock
cycles.
In the SAA1575HL, all of the data read and write cycles are
preceded by an internal Arithmetic and Logic Elements
(ALEs) cycle (as in any standard 80C51 system).
The multiplexed address/data bus and the ALE signal are
not available externally. However, for clarity, these are
illustrated in Figs 3 to 6.
handbook, full pagewidth
XTAL1
ALE
address/
data
address bus
RD
DMCS
address
external data
address
internal
signals
MHB462
The timing is configurable under firmware control.
Fig.3 Example of external data read (standard firmware).
1999 Jun 04
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