SAA1575HL Datasheet, PDF (12/56 Pages) NXP Semiconductors – Global Positioning System GPS baseband processor

Philips Semiconductors
Global Positioning System (GPS)
baseband processor
Product specification
SAA1575HL
7 FUNCTIONAL DESCRIPTION
7.1 Overview
The function of the SAA1575HL is to accept any IF data
(1 or 2-bit) from a front-end RF IC (such as the
UAA1570HL) and provide a serial NMEA compatible GPS
position and time output. The IF input is sampled
synchronously with the front-end reference clock, SCLK.
Data is decoded from the IF input stream by one of eight
parallel correlators which allow up to eight satellites to be
tracked at one time. The acquisition, allocation and
tracking of the satellites is performed under firmware
control by the on-chip processor.
In addition to the SAA1575HL and an appropriate
front-end IC (such as the UAA1570HL), the only external
components required to complete a functional GPS
receiver are some RAM, the firmware ROM and some
discrete devices to control the power supplies. The need
for external glue logic is eliminated by various chip-select
functions implemented on the SAA1575HL.
The SAA1575HL also contains an optional independent
Real-Time Clock (RTC) which requires a separate
32.768 kHz crystal. This can be set to GPS time by the
processor and enables fast re-acquisition (a warm start) of
satellites after power has been switched off. A separate
supply pin is provided to allow the RTC to be powered
while the rest of the IC is turned off.
The block diagram of the SAA1575HL is shown in Fig.1.
The IC consists of a processor core, its associated
peripherals, some internal memory and a series of GPS
correlators.
The processor core is based on an embedded Philips
80C51XA (known as the XA). The XA peripherals (UARTs,
timers, watchdog and general purpose I/Os) are termed
special function registers and are memory mapped in
parallel with an area of the data memory. They are
connected to the core by dedicated data and address
buses. The internal data memory is also connected to the
core by a dedicated bus.
The rest of the IC (the correlators, RTC and system
control) is mapped into the external data memory space.
The multiplexed data and address buses provided by the
XA core are separated by an on-chip latch to provide the
distinct 16-bit data bus and 19-bit address bus. These are
made available externally for connection to external
memory via the external bus interface.
The correlators, RTC and system control blocks are
memory mapped into the highest page of the 16 pages in
the XA data structure.
Both the RTC and the correlators are asynchronous to the
system clock, with synchronization being achieved by
firmware and interrupts.
7.2 The 80C51XA processor
The microcontroller core in the SAA1575HL is a Philips
design called the XA (eXtended Architecture) which is an
extended 80C51-like 16-bit microcontroller. This is largely
compatible with the 8051 but with various improvements.
The main features of the XA compared to the 8051 can be
summarized as follows:
• 16-bit versus 8-bit data processing
• 20-bit versus 16-bit address bus
• 3 clock instruction cycle versus 12 clock instruction
cycle
• 10 Mips versus 1 Mips
• 20 CPU registers versus 1 accumulator
• All 20 CPU registers in the XA can be used as the
accumulator register in the 8051
• 16 × 16 multiplication in 12 clocks, ³²â„₁₆ division in
22 clocks
• New type of instructions such as normalization, sign
extension and trap
• Multi-tasking support versus no multi-tasking support.
7.3 The GPS correlators
The correlator block forms the GPS specific hardware for
correlating with the direct sequence spread spectrum GPS
signals. The 8 identical correlators share the 2-bit IF input
and the sample clock of the Analog-to-Digital Converter
(ADC) of the front-end. The input signal is the 50 bits/s
GPS data spread by the 1.023 Mbits/s PN code and
modulated by the residual carrier. The residual carrier
frequency is composed of the Doppler frequency and the
receiver local oscillator frequency offset.
To recover the GPS data and find the accurate timing of
the received data for GPS navigation from the low-level (as
low as −130 dBm) GPS signal, the residual carrier
frequency and phase have to be found by a Phase-Locked
Loop (PLL) with minimum tracking phase error.
The starting position of the PN code in the received signal
is found by correlation within a Delay-Locked Loop (DLL).
The channel correlator includes a local numerically
controlled oscillator and a programmable local PN code
generator with the phase rotation and correlation circuit.
1999 Jun 04
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