SAA1575HL Datasheet, PDF (20/56 Pages) NXP Semiconductors – Global Positioning System GPS baseband processor

Philips Semiconductors
Global Positioning System (GPS)
baseband processor
Product specification
SAA1575HL
7.7.1 PROGRAM MEMORY CHIP SELECT
This signal (PMCS) is an active LOW strobe used to
enable the output of the external code memory. It remains
HIGH when a read code is not in progress.
7.7.2 DATA MEMORY CHIP SELECT
This signal (DMCS) is an active LOW strobe used to
enable the external data memory. The SAA1575HL
hardware supports two distinct modes of operation of this
signal (selected in firmware) designed for optimum power
or optimum speed. The standard Philips firmware is
configured for optimum power.
DMCS is taken LOW during an external data read or write
operation to segments 0 to 14 of the memory map.
To prevent the corruption of external data memory, the
DMCS pin is driven on the backup supply voltage and will
be held HIGH once the PWRFAIL signal has been
asserted LOW.
With the standard Philips firmware, the DMCS signal is
gated by the external access read and write strobes. This
should significantly reduce the power consumption of the
external RAM but may require the use of a slightly faster
external memory (depending on clock speed and details of
the external memory used).
7.7.3 READ STROBE
This signal (RD) is an active LOW strobe used to indicate
that the XA is expecting data from the external bus.
7.7.4 WRITE LOW BYTE STROBE
This signal (WRL) is an active LOW strobe used to indicate
that the XA is performing an external write. This strobe
only applies to the lower data byte of the 16-bit data word,
allowing byte writes to be performed from the 16-bit data.
This strobe will also be taken LOW for word write
operations.
7.7.5 WRITE HIGH BYTE STROBE
This signal (WRH) is an active LOW strobe used to
indicate that the XA is performing an external write. This
strobe only applies to the higher data byte of the 16-bit
data word, allowing byte writes to be performed from the
16-bit data. This strobe will also be taken LOW for word
write operations.
7.8 Backup supplies and reset
The SAA1575HL is designed to operate correctly in
situations when the main power supply fails. In addition to
the main core and peripheral power supplies, separate
pins are provided for backup core and peripheral supplies
which enable critical (and low-power) functions to be
maintained during the loss of main power. There is also an
on-chip reset timer which will aid the design of a full
power-down strategy.
7.8.1 SUPPLY DOMAINS
To allow for the use of inexpensive 5 V external
components, the periphery of the SAA1575HL can be
powered with a higher voltage than the core. Therefore
there is a distinction between the core and peripheral
power supplies. In addition, there is the need to maintain
certain functionality on a low-power supply in the event of
main power failure. Therefore there are 2 additional
supplies required for so-called backup operation. Thus
there are four distinct power supply domains, two for the
core supplies and two for the peripheral supplies.
Table 1 Supply domains
SUPPLY DESCRIPTION
PURPOSE
V_CC(core) main core
supply (3 V)
provides power for all core
circuits, excluding those
mentioned below
V_CC(P)
main peripheral provides power for all pins,
supply
excluding those mentioned
(3 to 5 V)
below
V_CC(R)
RTC core
supply
(2.4 to 3 V)
powers the real-time clock,
the 32 kHz oscillator and
the 32 kHz de-bounce
circuit; it also produces the
signals for DMCS, PWRM
and PWRB
V_CC(B)
backup
peripheral
supply
(2.4 to 5 V)
provides power for the
following pins: DMCS,
PWRM, PWRB and
PWRFAIL
In normal operation, the backup core and pad supplies
should be provided from the main power supply rather than
a low-capacity battery since the power drawn on the
backup supplies while the processor is operating may be
significant. Two output pins, PWRM and PWRB are
provided to control this switching.
1999 Jun 04
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