SAA1575HL Datasheet, PDF (24/56 Pages) NXP Semiconductors – Global Positioning System GPS baseband processor

Philips Semiconductors
Global Positioning System (GPS)
baseband processor
Product specification
SAA1575HL
7.8.3 SYSTEM RESET CONTROL
The SAA1575HL contains an internal timer and control
logic to perform various system reset tasks. Control of this
logic is by three external pins, PWRDN, PWRFAIL, and
RSTIME. This allows the system designer to set the
voltage thresholds at which the system goes into and
comes out of reset.
7.8.3.1 The reset timer
The heart of the reset system is a 20-bit counter with
asynchronous reset, clocked from the XTAL1 system
clock. The reset counter is asynchronously reset if the
PWRFAIL pin is LOW. Once reset, the counter will only be
enabled once both PWRFAIL and PWRDN go HIGH. This
prevents the SAA1575HL from leaving the reset state until
both power detect inputs have flagged the power system
as healthy.
The internal reset signal is generated by decoding the
reset counter. The decode value, and hence the time
delay, is controlled by the reset time control pin, RSTIME.
Table 3 Reset time control
RSTIME
INPUT
1
0
NUMBER OF
CYCLES BEFORE
RESET
DE-ASSERTED
294 912
288
TIME DELAY
(f_XTAL1 = 30 MHz)
9.8 ms
9.6 µs
The internal reset is de-asserted a given number of XTAL1
clock cycles after PWRFAIL and PWRDOWN go HIGH.
It is suggested that for most applications RSTIME should
be held HIGH, giving a reset time of approximately 10 ms.
This would be needed to allow the on-chip oscillator to
stabilize after power-up. The shorter reset time can be
used for applications using an external XTAL1 clock signal
which does not need a long stabilization period.
It is important that PWRFAIL should be LOW during
power-up of the IC to give the correct reset.
7.8.3.2 Overall reset operation
The assertion of the reset signal (by means already
described) will cause the following to occur:
• Internal XA processor reset
• Internal registers reset
• Data bus pins set to be inputs
• Read and write strobes de-asserted
• GPIO pins set to be inputs
• On-chip XTAL1 oscillator enabled.
7.8.3.3 CPU reset operation
Assuming that the correct external PWRFAIL sequence is
generated on power-up, the internal XA will receive the
correct reset signal from the on-chip reset block. If the
proper PWRFAIL is not performed, the operation of the
on-chip reset block cannot be guaranteed and the XA may
fail wholly or in part.
The embedded XA requires a minimum length of reset to
complete the various tasks. This minimum length is
guaranteed by the on-chip reset block. The only restriction
on the length of the pulse is that is should be long enough
to be asynchronously detected by the SAA1575HL
(typically 10 ns).
The embedded CPU can also be reset by the watchdog
timer (this may be disabled on some custom firmware
revisions).
7.8.4 POWER SAVING MODES
The SAA1575HL supports two power saving modes; Idle
mode and sleep mode. Both modes are selected by
firmware (or message over the serial link if included in the
firmware). In addition, the input to any of the correlators
can be inhibited individually (by firmware) which will
reduce the power consumed by the block to only the clock
tree dissipation.
1999 Jun 04
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