SAA1575HL Datasheet, PDF (21/56 Pages) NXP Semiconductors – Global Positioning System GPS baseband processor

Philips Semiconductors
Global Positioning System (GPS)
baseband processor
Product specification
SAA1575HL
The power consumption of the SAA1575HL in the
power-down mode is minimal since no outputs are
changing. The only active circuit in power-down is the
real-time clock.
Isolation between the power domains is controlled by the
PWRFAIL input pin. This must be driven LOW in a
power-failure situation to ensure that the backup domains
are isolated from the main supply domains. If this is not
done, it is possible that the registers contained in the
backup supply domain will be corrupted as the main supply
is cycled. It is also possible that under these
circumstances a high backup supply current will be drawn
(depending on details of the external supply circuitry).
7.8.2 POWER-DOWN DESIGN STRATEGY
In power-down operation the main supplies are assumed
to have failed. The backup core and pad supplies should
be switched to backup power. The detection of the power
failure and the power supply switching is the responsibility
of the user. However, the SAA1575HL does provide
several functions to aid this task.
The power-down and power-fail operations of the
SAA1575HL are controlled by two inputs, PWRDN and
PWRFAIL, which are assumed to be connected to external
voltage comparators. The use of external comparators
allows the voltage thresholds to be set by the system
designer. It also allows a certain amount of flexibility as to
which supplies are monitored for power failure.
7.8.2.1 Power-down control signals
The power-down control signal pins (see Table 2) are
either inputs or outputs associated with the SAA1575HL
power control. The descriptions are for the intended use of
the control signals in a normal application.
For a correct reset to occur, it is important that PWRFAIL
should be held LOW as long as minimum voltages have
been established on all four of the power supply domains.
If this is not done various serious consequences may
occur, including main oscillator failure, a high supply
current state, a processor crash or RTC register
corruption.
Table 2 Power-down control signals
SIGNAL
PWRDN
PWRFAIL
RSTIME
DMCS
PWRM
PWRB
FUNCTION
Power-down indicator: this should be driven LOW by an external comparator to indicate impending
power failure. Internally it sends an interrupt to the processor used to initiate a power-fail routine. At the
end of this routine the standard firmware forces the processor into reset. This also inhibits the external
RAM chip select. Reset is only de-asserted a set time after both PWRDN and PWRFAIL go HIGH,
controlled by the RSTIME input.
Power fail indicator: this should be driven LOW by an external comparator to indicate immediate power
failure. Internally it forces immediate reset of the processor, isolation of the RTC and inhibition of the
external RAM chip select. It also controls the power switch outputs PWRB and PWRM. Reset is only
de-asserted a set time after both go HIGH, controlled by the RSTIME input.
Reset timer control: this sets the time delay between de-assertion of both PWRDN and PWRFAIL and
the de-assertion of the processor reset. If HIGH, the delay is approximately 10 ms. If LOW the delay is
approximately 10 µs.
External RAM chip select: this is driven via the backup supplied core and pads. In power-down this is
isolated from the rest of the IC and the output held HIGH to prevent corruption of the external RAM.
Main power supply control: in normal operation this is held LOW. This can be used to switch the main
supplies to all of the supply input pins. In normal operation the backup pad supply pin should be driven
by the main supply and the backup core supply pins should be driven by the main core supply. When the
IC goes into power-down mode this output goes HIGH. In power-down the backup supply pins should be
driven by their appropriate supplies.
Backup power supply control: this is the inverse of PWRM
1999 Jun 04
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