SAA1575HL Datasheet, PDF (14/56 Pages) NXP Semiconductors – Global Positioning System GPS baseband processor

Philips Semiconductors
Global Positioning System (GPS)
baseband processor
Product specification
SAA1575HL
handbook, full pagewidth
XTAL1
ALE
address/
data
address bus
WRH / WRL
DMCS
address
external data
address
internal
signals
MHB463
The timing is configurable under firmware control.
Fig.4 Example of external data write (standard firmware).
7.4.2 CODE MEMORY SPACE
The SAA1575HL has no internal code memory. The GPS
solution firmware resides in external memory. With the
standard Philips firmware, a ROM with a maximum access
time of 100 ns is required.
The classic operation of a multiplexed address/data bus
involves an address being set-up for every bus cycle.
The internal ALE signal is used to latch the address prior
to the cycle on which the data is set-up. An example of the
resulting timing is illustrated in Fig.5.
The SAA1575HL does not require an internal ALE cycle for
each code fetch. The lowest 3 address lines are not
multiplexed with the data lines and so these can be used
to incrementally read code locations.
The XA core can therefore issue up to 8 word reads
through sequential code memory for each ALE cycle. This
is termed a burst code read. An example of the resulting
timing is illustrated in Fig.6.
Any type of branch or jump in the program may require a
code fetch in a non-sequential manner and a new ALE
cycle will be needed. This may occur at any stage in a
code read. Thus the length of the read strobe in a burst
read is not necessarily an integer multiple of the individual
code read length.
1999 Jun 04
14