SAA1575HL Datasheet, PDF (10/56 Pages) NXP Semiconductors – Global Positioning System GPS baseband processor

Philips Semiconductors
Global Positioning System (GPS)
baseband processor
Product specification
SAA1575HL
SYMBOL PIN
RFLE
91
IF2
92
IF1
93
GPIO2
94
GPIO1
95
GPIO0
96
n.c.
97
RCLK
98
TEST1
99
TEST2
100
I/O
DESCRIPTION
O RFIC setup latch: output used to latch the RFIC set-up into the active UAA1570HL
control registers
I MSB IF input: MSB of the 2-bit GPS digital IF signal input. Clocked in on the rising
edge of SCLK. If only a 1-bit IF input is available this input should be held HIGH.
I LSB IF input: LSB of the 2-bit GPS digital IF signal input. Clocked in on the rising
edge of SCLK.
I/O GPIO bit 2: standard general purpose I/O mapped into the segment 15 of the address
space. The top 4 bits can be used as the XA external timer control access pins
(T0, T1, T2 and T2EX).
I/O GPIO bit 1: standard general purpose I/O mapped into the segment 15 of the address
space. The top 4 bits can be used as the XA external timer control access pins
(T0, T1, T2 and T2EX).
I/O GPIO bit 0: standard general purpose I/O mapped into the segment 15 of the address
space. The top 4 bits can be used as the XA external timer control access pins
(T0, T1, T2 and T2EX).
O Not connected: do not connect
I Reference clock: input from the TXCO reference. Not used internally. This is divided
under firmware control to produce the sample clock, SCLK, used to gate the IF inputs.
I Test pin: connect to pin 100
O Test pin: connect to pin 99
1999 Jun 04
10