PLC42VA12 Datasheet, PDF (9/20 Pages) NXP Semiconductors – CMOS programmable multi-function PLD 42 × 105 × 12

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLD
(42 × 105 × 12)
Product specification
PLC42VA12
OUTPUT MACRO CELL (OMC)
FROM AND ARRAY
O
F_C CONTROL
LOAD PRESET RESET
CK OE
E
FROM OR ARRAY
JK/D
MUX
FROM OR ARRAY
TO AND ARRAY
FROM OR ARRAY
P
R
J
CK
CLOCK ⁰
SELECT
MUX ₁
K
Q
1
M
(REGISTER BYPASS)
OUTPUT
SELECT
MUX
0
1
OUTPUT ENABLE
SELECT MUX
CLK
M
TO AND ARRAY
Output Macro Cell Configuration
Philips Semiconductors unique Output Macro
Cell design represents a significant
advancement in the configurability of
multi-function Programmable Logic Devices.
The PLC42VA12 has 10 programmable
Output Macro Cells. Each can be individually
programmed in any of 5 basic configurations:
• Dedicated I/O (combinatorial) with
feedback to AND array
• Dedicated Input
• Combinatorial I/O with feedback and
Buried Register with feedback (register
bypass)
• Registered Input
• Registered Output with feedback
Each of the registered options can be further
customized as J-K type or D-type, with either
an internally derived clock (from the AND
array) or clocked from an external source.
With these additional programmable options,
it is possible to program each Output Macro
Cell in any one of 14 different configurations.
These 14 configurations, combined with the
fully programmable OR array, make the
PLC42VA12 the most versatile and silicon
efficient of all the Output Macro Cell-type
PLDs.
The most significant Output Macro Cell
(OMC) feature is the implementation of the
register bypass function. Any of the 10 J-K/D
registers can be individually bypassed, thus
creating a combinatorial I/O path from the
AND array to the output pin. Unlike other
Output Macro Cell-type devices, the register
in the OMC is fully functional as a buried
register. Furthermore, both the combinatorial
I/O and the buried register have separate
input paths (from the AND array) and
separate feedback paths (to the AND array).
This feature provides the capability to operate
the buried register independently from the
combinatorial I/O.
The PLC42VA12 is ideally suited for both
synchronous and asynchronous logic
functions. Eleven clock sources – 10 driven
from the AND array and one from an external
source – make it possible to design
synchronous state machine functions,
event-driven state machine functions and
combinatorial (asynchronous) functions all on
the same chip.
Sophisticated control functions support
individual OE control and Reset functions
from the AND array. OE control is also
available from the I9/OE pin. Register Preset
and Load functions are controlled from the
AND array, in 2 banks of 4 for OMCs M1 –
M8. Output Macro Cells M0 and M9 have
individual Preset and Load Control terms.
Output Polarity for the combinatorial I/O
paths is configurable via 12 programmable
EX-OR gates. The output of each register
can be configured as inverting (active Low) or
non-inverting (active High) via manipulation
of the logic equations.
The output of each buried register can also
be configured as inverting or non-inverting via
the input buffer which feeds back to the AND
array.
October 22, 1993
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