PLC42VA12 Datasheet, PDF (12/20 Pages) NXP Semiconductors – CMOS programmable multi-function PLD 42 × 105 × 12

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLD
(42 × 105 × 12)
Product specification
PLC42VA12
OUTPUT MACRO CELL CONFIGURATION OPTIONS
REGISTER SELECT OPTIONS
REGISTER SELECT OPTIONS
FROM
OR ARRAY
TO
AND ARRAY
D (OR J) CK
(K)
Q
CLOCK
OPTIONS
OMC
CONFIG.
OPTIONS
FROM
OR ARRAY
D (OR J) CK
(K)
Q
CLOCK
OPTIONS
TO
AND ARRAY
M
FROM
OR
ARRAY
COMBINATORIAL OPTIONS
OUTPUT
CONTROL
M
OPTIONS
OMC CONFIGURATION
REGISTERED OUTPUT
(D or JK)
CODE
A
OMC CONFIGURATION
COMBINATORIAL OUTPUT
WITH BURIED REGISTER
(D or JK)
CODE
•
L
D
CK
Q
TO AND
ARRAY
M
CLOCK
OPTIONS
OUTPUT
CONTROL
OPTIONS
OMC CONFIGURATION
REGISTERED INPUT
LOAD CONTROL P-TERM
CODE
A or •⁵
H⁶
Notes on page 87.
OMC Configuration Options
Each OMC can be configured as a Registered
Output with feedback, a Registered Input or a
Combinatorial I/O with Buried Register.
Dedicated Input and dedicated I/O
configurations are also possible.
When the Combinatorial I/O option is
selected, (the Register Bypass option), the
Buried Register remains 100% functional, with
its own inputs from the AND array and a
separate feedback path. This unique feature is
ideal for designing any type of state machine;
synchronous Mealy-types that require both
Buried and Output Registers, or asynchronous
Mealy-types that require buried registers and
combinatorial output functions. Both
synchronous and asynchronous Moore-type
state machines can also be easily
accommodated with the flexible OMC
structure.
Note that an OMC can be configured as
either a Combinatorial I/O (with Buried
Register) or a Registered Output with
feedback and it can still be used as a
Registered Input. By disabling the outputs via
any OE control function, the M pin can be
used as an input. When the Load Control
P-term is asserted HIGH, the register is
preloaded from the M pin(s). When the L_C
P-term is Active-Low and the output is
enabled, the OMC will again function as
configured (either a combinatorial I/O or a
registered output with feedback). This feature
is suited for synchronizing input signals prior
to commencing a state sequence.
October 22, 1993
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