PLC42VA12 Datasheet, PDF (8/20 Pages) NXP Semiconductors – CMOS programmable multi-function PLD 42 × 105 × 12

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLD
(42 × 105 × 12)
Product specification
PLC42VA12
AC ELECTRICAL CHARACTERISTICS (Continued)
0°C ≤ T_amb ≤ +75°C, 4.75V ≤ V_CC ≤ 5.25V; R₁ = 238Ω, R₂ = 170Ω
TEST²
PLC42VA12
SYMBOL
PARAMETER
Frequency of Operation
FROM
TO
CONDITION
(C_L (pF))
MIN
TYP¹ MAX
UNIT
f_CK1
f_CK2
f_MAX1
f_MAX2
f_MAX33
Dedicated clock frequency
P-term clock frequency
Registered operating frequency;
Dedicated clock (t_IS1 + t_CKO1)
Registered operating frequency;
P-term clock (t_IS2 + t_CKO2)
Register preload operating
frequency; Dedicated clock
(t_IS3 + t_CKO1)
C+
C+
(I, B, M) +/–
(I, B, M) +/–
(M) +/–
C+
C+
(M) +/–
(M) +/–
(M) +/–
50
50
100
50
33
71.4
50
25
34.5
50
21.3 32.3
50
37
60.6
MHz
MHz
MHz
MHz
MHz
f_MAX43
Register preload operating
frequency; P-term clock
(t_IS4 + t_CKO2)
(M) +/–
(M) +/–
50
34.5 58.8
MHz
f_MAX53
Registered operating frequency
with complement array;
Dedicated clock (t_IS5 + t_CKO1)
(I, B, M) +/–
(M) +/–
50
14.9 21.3
MHz
f_MAX63
Registered operating frequency
with complement array;
P-term clock (t_IS6 + t_CKO2)
(I, B, M) +/–
(M) +/–
50
14.9 20.8
MHz
NOTES:
1. All typical values are at V_CC = 5V, T_amb = +25°C. These limits are not tested/guaranteed.
2. Refer also to AC Test Conditions (Test Load Circuit).
3. These limits are not tested, but are characterized periodically and are guaranteed by design.
4. For 3-State output; output enable times are tested with C_L = 50pF to the 1.5V level, and S₁ is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with C_L = 5pF. High-to-High impedance tests are made to an output
voltage of V_T = (V_OH – 0.5V) with S₁ open, and Low-to-High impedance tests are made to the V_T = (V_OL + 0.5V) level with S₁ closed.
BLOCK DIAGRAM
65 X 105 PROGRAMMABLE AND ARRAY
I1
64 LOGIC TERMS
I8
41 CONTROL TERMS
COMPLEMENT
64 X 32
PROGRAMMABLE
OR ARRAY
JK/D
MUX
JP R L D
OMC OE
(10)
Q
K
BYPASS
Q
CK
MUX
MUX
October 22, 1993
80
I0/CLK
I9/OE
M0 – M9
B0 – B1