PLC42VA12 Datasheet, PDF (17/20 Pages) NXP Semiconductors – CMOS programmable multi-function PLD 42 × 105 × 12

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLD
(42 × 105 × 12)
TIMING DIAGRAMS (Continued)
I, B
(LOAD SELECT)
1.5V
I, B, OE TERM OR OE PIN
(OUTPUT ENABLE)
1.5V
L
1.5V
t_OE1,2
+3V
1.5V
0V
+3V
0V
M
(INPUT)
+3V
V_T (FORCED D_IN) 1.5V
0V
P-TERM OR
ÇÇÇÇÇÇÇÇÇÇÇ _{EXTERNAL CK}
ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ _Q
t_OD1,2
t_IS3,4 t_IH3,4
t_CKL
t_CKH
t_IH3,4
(D_IN)
+3V
0V
Flip-Flop Input Mode (Preload)
I, B, M
(INPUTS)
P-TERM OR
EXTERNAL CK
PRESET/RESET
(I, B, M INPUTS)
1.5V
ÇÇÇÇÇÇÇÇÇÇÇÇ_1.5V
ÇÇÇÇ t_IS*
t_IS
t_CKO
+3V
0V
+3V
0V
+3V
1.5V
1.5V
0V
t_PRH
Q
(PRESET)
(RESET)
M
(OUTPUTS)
t_PRO
1.5V
(RESET)
(PRESET)
1.5V
V_OH
V_OL
*Preset and Reset functions override Clock. However, M outputs may glitch with
the first positive Clock Edge if t_IS cannot be guaranteed by the user.
Asynchronous Preset/Reset
V_CC
ÇÇÇÇÇÇÇÇ _M
ÇÇÇÇÇÇÇÇ _(OUTPUTS)
4.5V
t_PPR
1.5V
1.5V
t_CKO1,2
+5V
0V
V_OH
V_OL
I, B, M
(INPUTS)
P-TERM OR
EXTERNAL CK
+3V
1.5V
1.5V
0V
t_IH
t_IS
+3V
1.5V
1.5V
1.5V
0V
t_IS
t_CKH
t_CKL
t_CK1,2
Power-On Reset
October 22, 1993
89
Product specification
PLC42VA12
TIMING DEFINITIONS (Continued)
SYMBOL PARAMETER
Required delay between positive
t_IH2 transition of P-term Clock and
end of valid input data.
Required delay between positive
t_IH3
transition of External Clock and
end of valid input data when us-
ing Preload Inputs (from M pins).
Required delay between positive
t_IH4
transition of P-term Clock and
end of valid input data when us-
ing Preload Inputs (from M pins).
Required delay between begin-
t_IS1 ning of valid input and positive
transition of External Clock.
Required delay between begin-
t_IS2 ning of valid input and positive
transition of P-term Clock input.
Required delay between
t_IS3
beginning of valid Preload input
(from M pins) and positive
transition of External Clock.
Required delay between
t_IS4
beginning of valid Preload input
(from M pins) and positive
transition of P-term Clock input.
Required delay between
t_IS5
beginning of valid input through
Complement Array and positive
transition of External Clock.
Required delay between
t_IS6
beginning of valid input through
Complement Array and positive
transition of P-term Clock input.
Delay between beginning of
t_OE1
Output Enable signal (Low) from
/OE pin and when Outputs
become valid.
Delay between beginning of
t_OE2
Output Enable signal (High or
Low) from OE P-term and when
Outputs become valid.
Delay between beginning of
t_OD1
Output Enable signal (HIGH) from
/OE pin and when Outputs
become disabled.
Delay between beginning of
t_OD2
Output Enable signal (High or
Low) from OE P-term and when
Outputs become disabled.
Delay between beginning of valid
t_PD input and when the Outputs be-
come valid (Combinatorial Path).
t_PRH
t_PRO
Width of Preset/Reset Pulse.
Delay between beginning of valid
Preset/Reset Input and when the
registered Outputs become
Preset (“1”) or Reset (“0”).
Delay between V_CC (after
power-up) and when flip-flops
t_PPR become Reset to “0”. Note:
Signal at Output (M pin) will be
inverted.