PLC42VA12 Datasheet, PDF (15/20 Pages) NXP Semiconductors – CMOS programmable multi-function PLD 42 × 105 × 12

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLD
(42 × 105 × 12)
Product specification
PLC42VA12
LOGIC IMPLEMENTATION (Continued)
OUTPUT MACRO CELL CONFIGURATIONS
OUTPUT MACRO CELL
CONFIGURATION
REGISTER SELECT
FUSE
Combinatorial I/O with Buried D-type register
External clock source
A
P-term clock source
A
Combinatorial I/O with Buried J-K type register
External clock source
•
P-term clock source
•
Registered Output (D-type) with feedback
External clock source
A
P-term clock source
A
Registered Output (J-K type) with feedback
External clock source
•
P-term clock source
•
Registered Input (Clocked Preload) with feedback
External clock source
A
P-term clock source
A
PROGRAMMING CODES
OMC CONFIGURATION
FUSE
POLARITY
FUSE
•
H or L
•
H or L
•
H or L
•
H or L
A
N/A
A
N/A
A
A
A or •⁵
A or •⁵
N/A
N/A
Optional⁵
Optional⁵
CLOCK
FUSE
A
•
A
•
A
•
A
•
A
•
OUTPUT ENABLE CONTROL⁸
CONFIGURATION
OUTPUT CONTROL FUSES
OE CONTROL FUSE
En FUSES
CONTROL SIGNAL
OMC controlled by /OE pin
A
Output Enabled
Output Disabled
OMC controlled by P-term
•
Output Enabled
Output Disabled
A
A or 0
Low
High
High
Low
Output always Enabled
A
0
Not Applicable
NOTES:
1. This is the initial (unprogrammed) state of the device.
2. Any gate will be unconditionally inhibited if both the TRUE and COMPLEMENT fuses are left intact.
3. To prevent oscillations, this state is not allowed for Complement Array fuse pairs that are coupled to active product terms.
4. The OMC Configuration fuse must be programmed as Combinatorial I/O in order to make use of the Polarity Option.
5. Regardless of the programmed state of the OMC Configuration fuse, an OMC can be used as a Registered Input. Note that the Load Control
P-term must be asserted Active-High.
6. Output must be disabled.
7. Program code definitions:
A = Active (unprogrammed fuse)
0, • = Inactive (programmed fuse)
– = Don’t Care (both TRUE and COMPLEMENT fuses unprogrammed)
H = Active-High connection
L = Active-Low connection
8. OE control for B0 and B1 (Pins 10 and 11) is from the AND array only.
October 22, 1993
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