PLC42VA12 Datasheet, PDF (1/20 Pages) NXP Semiconductors – CMOS programmable multi-function PLD 42 × 105 × 12

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLD
(42 × 105 × 12)
Product specification
PLC42VA12
DESCRIPTION
The new PLC42VA12 CMOS PLD from
Philips Semiconductors exhibits a unique
combination of the two architectural concepts
that revolutionized the PLD marketplace.
The Philips Semiconductors unique Output
Macro Cell (OMC) embodies all the
advantages and none of the disadvantages
associated with the “V” type Output Macro
Cell devices. This new design, combined with
added functionality of two programmable
arrays, represents a significant advancement
in the configurability and efficiency of
multi-function PLDs.
The most significant improvement in the
Output Macro Cell structure is the
implementation of the register bypass
function. Any of the 10 J-K/D registers can be
individually bypassed, thus creating a
combinatorial I/O path from the AND array to
the output pin. Unlike other “V” type devices,
the register in the PLC42VA12 Macro Cell
remains fully functional as a buried register.
Both the combinatorial I/O and buried register
have separate input paths (from the AND
array). In most V-type architectures, the
register is lost as a resource when the cell is
configured as a combinatorial I/O. This
feature provides the capability to operate the
buried register independently from the
combinatorial I/O.
The PLC42VA12 is an EPROM-based CMOS
device. Designs can be generated using
Philips Semiconductors SNAP PLD design
software packages or one of several other
commercially available JEDEC standard PLD
design software packages.
FEATURES
• High-speed EPROM-based CMOS
Multi-Function PLD
– Super set of 22V10, 32VX10 and
20RA10 PAL® ICs
• Two fully programmable arrays eliminate
“P-term Depletion”
– Up to 64 P-terms per OR function
• Improved Output Macro Cell Structure
– Individually programmable as:
* Registered Output with feedback
* Registered Input
* Combinatorial I/O with Buried Register
* Dedicated I/O with feedback
* Dedicated Input (combinatorial)
– Bypassed Registers are 100% functional
with separate input and feedback paths
– Individual Output Enable control
functions
* From pin or AND array
• Reprogrammable – 100% tested for
programmability
• Eleven clock sources
• Register Preload and Diagnostic Test Mode
Features
• Security fuse
APPLICATIONS
• Mealy or Moore State Machines
– Synchronous
– Asynchronous
• Multiple, independent State Machines
• 10-bit ripple cascade
• Sequence recognition
• Bus Protocol generation
• Industrial control
• A/D Scanning
PIN CONFIGURATIONS
FA and N Pack-
ages
I0/CLK ¹
I1 ²
I2 ³
I3 ⁴
I4 ⁵
I5 ⁶
I6 ⁷
I7 ⁸
I8 ⁹
B0 ¹⁰
B1 ¹¹
GND 12
24 V_CC
23 _M9
22 _M8
21 _M7
20 _M6
19 _M5
18 _M4
17 _M3
16 _M2
15 _M1
14 _M0
13 _I9/OE
N = Plastic DIP (300mil-wide)
FA = Ceramic DIP with Quartz Window (300mil-wide)
A Package
I0/
I2 I1 CLK N/C V_CC M9 M8
4 3 2 1 28 27 26
I3 ⁵
25 _M7
I4 ⁶
24 _M6
I5 ⁷
23 _M5
N/C 8
22 N/C
I6 ⁹
21 _M4
I7 ¹⁰
20 _M3
I8 ¹¹
19 _M2
12 13 14 15 16 17 18
B0 B1 GND N/C I9/ M0 M1
OE
A = Plastic Leaded Chip Carrier (450mil-square)
ORDERING INFORMATION
DESCRIPTION
24-Pin Ceramic Dual In-Line with window,
Reprogrammable (300mil-wide)
24-Pin Plastic Dual In-Line,
One Time Programmable (300mil-wide)
28-Pin Plastic Leaded Chip Carrier,
One Time Programmable (450mil-wide)
ORDER CODE
PLC42VA12FA
PLC42VA12N
PLC42VA12A
DRAWING NUMBER
1478A
0410D
0401F
PAL is a registered trademark of Advanced Micro Devices, Inc.
October 22, 1993
73
853–1414 11164