PLC42VA12 Datasheet, PDF (16/20 Pages) NXP Semiconductors – CMOS programmable multi-function PLD 42 × 105 × 12

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLD
(42 × 105 × 12)
Product specification
PLC42VA12
TIMING DIAGRAMS
I, B, M
(INPUTS)
P-TERM CK
(I, B, M)
M
(OUTPUTS)
I, B, M, OE TERM OR
OE PIN
(OUTPUT ENABLE)
1.5V
1.5V
t_IH2
1.5V
t_IS2,6
1.5V
1.5V
t_IS2,6
t_CKH2
t_CKL2
1.5V
t_CKO2
t_RP2,6
1.5V
t_OE1,2
V_T
t_OD1,2
1.5V
Flip-Flop Outputs with P-term Clock
+3V
0V
+3V
0V
V_OH
V_OL
+3V
0V
I, B, M
(INPUTS)
EXTERNAL CK
M
(OUTPUTS)
I, B, M, OE TERM
OR OE PIN
(OUTPUT ENABLE)
1.5V
1.5V
t_IH1
1.5V
t_IS1,5
1.5V
1.5V
t_IS1,5
t_CKH1
t_CKL1
1.5V
t_CKO1
t_RP1,5
1.5V
t_OE1,2
V_T
t_OD1,2
1.5V
Flip-Flop Outputs with External Clock
+3V
0V
+3V
0V
V_OH
V_OL
+3V
0V
I, B
(INPUTS)
1.5V
B, M
(COMBINATORIAL
OUTPUTS)
I, B, M, OE TERM
OR OE PIN
(OUTPUT ENABLE)
ÇÇÇÇtPDÇÇÇÇÇÇÇÇÇÇÇÇ 1.5V
t_OE2
+1.5V
Gated Outputs
t_OD2
+1.5V
+3V
0V
V_OH
V_T
V_OL
+3V
0V
October 22, 1993
88
TIMING DEFINITIONS
SYMBOL PARAMETER
f_CK1
f_CK2
t_CKH1
t_CKH2
t_CKL1
t_CKL2
t_CKO1
t_CKO2
t_RP1
t_RP2
t_RP3
t_RP4
t_RP5
t_RP6
f_MAX1
f_MAX2
f_MAX3
f_MAX4
f_MAX5
f_MAX6
t_IH1
Clock Frequency; External Clock
Clock Frequency; P-term Clock
Width of Input Clock Pulse;
External Clock
Width of Input Clock Pulse;
P-term Clock
Interval between Clock pulses;
External Clock
Interval between Clock Pulses;
P-term Clock
Delay between the Positive
Transition of External Clock and
when M Outputs become valid.
Delay between the Positive
Transition of P-term Clock and
when M Outputs become valid.
Delay between beginning of Valid
Input and when the M outputs
become Valid when using
External Clock.
Delay between beginning of Valid
Input and when the M outputs
become Valid when using P-term
Clock.
Delay between beginning of Valid
Input and when the M outputs
become Valid when using
Preload Inputs (from M pins) and
External Clock.
Delay between beginning of Valid
Input and when the M outputs
become valid when using
Preload inputs (from M pins) and
P-term Clock.
Delay between beginning of Valid
Input and when the M outputs
become Valid when using Com-
plement Array and External
clock.
Delay between beginning of Valid
Input and when the M outputs
become Valid when using Com-
plement Array and P-term Clock.
Minimum guaranteed Operating
Frequency; Dedicated Clock
Minimum guaranteed Operating
Frequency; P-term Clock
Minimum guaranteed Operating
Frequency using Preload;
Dedicated Clock (M pin to M pin)
Minimum guaranteed Operating
Frequency using Preload; P-term
Clock (M pin to M pin)
Minimum guaranteed Operating
Frequency using Complement
Array; Dedicated Clock
Minimum Operating Frequency
using Complement Array; P-term
Clock
Required delay between positive
transition of External Clock and
end of valid input data.