PLC42VA12 Datasheet, PDF (6/20 Pages) NXP Semiconductors – CMOS programmable multi-function PLD 42 × 105 × 12

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLD
(42 × 105 × 12)
Product specification
PLC42VA12
DC ELECTRICAL CHARACTERISTICS
0°C ≤ T_amb ≤ +75°C, 4.75V ≤ V_CC ≤ 5.25V
SYMBOL
PARAMETER
TEST CONDITION
MIN
Input voltage²
V_IL
Low
V_IH
High
Output voltage²
V_CC = MIN
V_CC = MAX
–0.3
2.0
V_OL
Low
V_OH
High
Input current
V_CC = MIN; I_OL = 16mA
V_CC = MIN; I_OH = –3.2mA
2.4
I_IL
Low
I_IH
High
Output current
V_IN = GND
V_IN = V_CC
I_O(OFF)
Hi-Z state
I_OS
Short-circuit^3,7
I_CC1
V_CC supply current (Active)⁴
I_CC2
V_CC supply current (Active)⁵
Capacitance
V_OUT = V_CC
V_OUT = GND
V_OUT = GND
I_OUT = 0mA, f = 15MHz⁶, V_CC = MAX
I_OUT = 0mA, f = 15MHz⁶, V_CC = MAX
C_I
Input
V_CC = 5V; V_IN = 2.0V
C_B
I/O
V_B = 2.0V
NOTES:
1. All typical values are at V_CC = 5V. T_amb = +25°C.
2. All voltage values are with respect to network ground terminal.
3. Duration of short–circuit should not exceed one second. Test one at a time.
4. Tested with V_IL = 0.45V, V_IH = 2.4V.
5. Tested with V_IL = 0V, V_IH = V_CC.
6. Refer to Figure 1, ∆I_CC vs Frequency (worst case). (Referenced from 15MHz)
The I_CC increases by 1.5mA per MHz for the frequency range of 16MHz up to 25MHz.
The I_CC remains at a worst case for the frequency range of 26MHz up to 37MHz.
The I_CC decreases by 1.0mA per MHz for the frequency range of 14MHz down to 1MHz.
The worst case I_CC is calculated as follows:
– All dedicated inputs are switching.
– All OMCs are configured as JK flip-flops in the toggle mode. . .all are toggling.
– All 12 outputs are disabled.
– The number of product terms connected does not impact the I_CC.
7. Refer to Figure 2 for ∆t_PD vs output capacitance loading.
LIMITS
TYP¹
MAX
UNIT
0.8
V
V_CC + 0.3
V
0.3
0.5
V
4.3
V
–1
–10
µA
+1
10
µA
1
10
µA
–1
–10
µA
–130
mA
90
120
mA
70
100
mA
12
pF
15
pF
+30
+25
+20
+15
+10
+5
0
–5
–10
–15
1
5
10 15 20 25 30 35 40
f(MHz)
Figure 1. ∆I_CC vs Frequency
(Worst Case) (Referenced from 15MHz)
6
5
4
3
2
1
0
–1
–2
0 20 40 60 80 100 120 140 160 180 200
OUTPUT CAPACITANCE LOADING (pF)
Figure 2. ∆t_PD vs Output
Capacitance Loading (Typical)
October 22, 1993
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