PLC42VA12 Datasheet, PDF (18/20 Pages) NXP Semiconductors – CMOS programmable multi-function PLD 42 × 105 × 12

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLD
(42 × 105 × 12)
Product specification
PLC42VA12
LOGIC FUNCTION
Q3 Q2 Q1 Q0
1010
STATE REGISTER
S_R PRESENT STATE
A⋅B⋅C⋅...
0001
S_{n + 1} NEXT STATE
SET Q₀: J₀ = (Q₂ ⋅ Q₁ ⋅ Q₀) ⋅ A ⋅ B ⋅ C . . .
K₀ = 0
RESET
Q₁: J₁
K₁
=
=
0
(Q₃
⋅
Q₂
⋅
Q₁
⋅
Q₀)
⋅
A
⋅
B
⋅
C
.
.
.
HOLD Q₂: J₂ = 0
K₂ = 0
RESET
Q₃:
J₃
K₃
=
=
(Q₃
(Q₃
⋅
⋅
Q₂
Q₂
⋅
⋅
Q₁
Q₁
⋅
⋅
Q₀)
Q₀)
⋅
⋅
A
A
⋅
⋅
B
B
⋅
⋅
C
C
.
.
.
.
.
.
NOTE:
Similar logic functions are applicable for D
mode flip-flops.
FLIP-FLOP TRUTH TABLE
OE L_n CK_n P_n R_n J K Q M
H
Hi-Z
L X X X X XXL H
L X X H L XXH L
L X X L H XXL H
L L ↑ L L LLQ Q
L L ↑ L L LHL H
L L ↑ L L HLH L
L L ↑ L L HHQ Q
H H ↑ L L L H L H*
H H ↑ L L H L H L*
+10V X ↑ X X L H L H**
X ↑ X X H L H L**
NOTES:
1. Positive Logic:
J-K = T₀ + T₁ + T₂ + ... + T₃₁
T_n = C ⋅ (I0 ⋅ I1 ⋅ I2...) ⋅ (Q0 ⋅ Q1...) ⋅
(B0 ⋅ B1...)
2. ↑ denotes transition for Low to High level.
3. X = Don’t care
4. * = Forced at M_n pin for loading the J-K
flip-flop in the Input mode. The load
control term, L_n must be enabled (HIGH)
and the p-terms that are connected to the
associated flip-flop must be forced LOW
(disabled) during Preload.
5. At P = R = H, Q = H. The final state of Q
depends on which is released first.
6. ** = Forced at F_n pin to load J/K flip-flop
(Diagnostic mode).
PLC42VA12 UNPROGRAMMED
STATE
A factory shipped unprogrammed device is
configured such that all cells are in a
conductive state.
The following are:
ACTIVE:
– OR array logic terms
– Output Macro Cells M1 – M8;
• D-type registered outputs (D = 0)
– External clock path
– Inputs: B0, B1, M0, M9
INACTIVE:
– AND array logic and control terms (except
flip-flop mode control term, F_C)
– Bidirectional I/O (B0, B1);
• Inputs are active. Outputs are 3-Stated
via the OE P-terms, D0 and D1.
• D-type registers (D = 0).
– Output Macro Cells M0 and M9;
• Bidirectional I/O, 3-Stated via the OE
P-terms, DM0 and DM9. The inputs are
active.
– P-term clocks
– Complement Array
– J-K Flip-Flop mode
PROGRAMMING AND
SOFTWARE SUPPORT
Refer to Section 9 (Development Software)
and Section 10 (Third-party Programmer/
Software Support) in this data handbook for
additional information.
ERASURE CHARACTERISTICS
(For Quartz Window Packages
Only)
The erasure characteristics of the
PLC42VA12 devices are such that erasure
begins to occur upon exposure to light with
wavelength shorter than approximately 4000
Angstroms (Å). It should be noted that
sunlight and certain types of fluorescent
lamps have wavelengths in the 3000 – 4000Å
range. Data shows that constant exposure to
room level fluorescent lighting could erase a
typical PLC42VA12 in approximately three
years, while it would take approximately one
week to cause erasure when exposed to
direct sunlight. If the PLC42VA12 is to be
exposed to these types of lighting conditions
for extended periods of time, opaque labels
should be placed over the window to prevent
unintentional erasure.
The recommended erasure procedure for the
PLC42VA12 is exposure to shortwave
ultraviolet light which has a wavelength of
2537 Angstroms (Å). The integrated dose
(i.e., UV intensity × exposure time) for
erasure should be a minimum of
15Wsec/cm². The erasure time with this
dosage is approximately 30 to 35 minutes
using an ultraviolet lamp with a
12,000µW/cm² power rating. The device
should be placed within one inch of the lamp
tubes during erasure. The maximum
integrated dose a CMOS EPLD can be
exposed to without damage is
7258Wsec/cm² (1 week @ 12000µW/cm²).
Exposure of these CMOS EPLDs to high
intensity UV light for longer periods may
cause permanent damage.
The maximum number of guaranteed
erase/write cycles is 50. Data retentions
exceeds 20 years.
October 22, 1993
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