PLC42VA12 Datasheet, PDF (7/20 Pages) NXP Semiconductors – CMOS programmable multi-function PLD 42 × 105 × 12

Philips Semiconductors Programmable Logic Devices
CMOS programmable multi-function PLD
(42 × 105 × 12)
Product specification
PLC42VA12
AC ELECTRICAL CHARACTERISTICS
0°C ≤ T_amb ≤ +75°C, 4.75V ≤ V_CC ≤ 5.25V; R₁ = 238Ω, R₂ = 170Ω
SYMBOL
PARAMETER
FROM
Set-up Time
t_IS1
t_IS2
t_IS33
t_IS43
t_IS53
Input; dedicated clock
Input; P-term clock
Preload; dedicated clock
Preload; P-term clock
Input through complement array;
dedicated clock
t_IS63
Input through complement array;
P-term clock
Propagation Delay
t_PD1
Propagation Delay
t_PD2
Propagation Delay with complement
array (2 passes)
t_CKO1
t_CKO2
t_RP1
t_RP2
t_RP33
t_RP43
t_RP53
t_RP63
t_OE1
t_OE2
Clock to Output; Dedicated clock
Clock to output; P-term clock
Registered operating period;
Dedicated clock (t_IS1 + t_CKO1)
Registered operating period;
P-term clock (t_IS2 + t_CKO2)
Register preload operating period;
Dedicated clock (t_IS3 + t_CKO1)
Register preload operating period;
P-term clock (t_IS4 + t_CKO2)
Registered operating period with comple-
ment array; dedicated clock (t_IS5 +
t_CKO1)
Registered operating period with
complement array; P-term clock
(t_IS6 + t_CKO2)
Output Enable; from /OE pin⁴
Output Enable; from P-term⁴
t_OD1
Output Disable; from /OE pin⁴
(I, B, M) +/–
(I, B, M) +/–
(M) +/–
(M) +/–
(I, B, M) +/–
(I, B, M) +/–
(I, B, M) +/–
(I, B,) +/–
CK+
(I, B, M) +/–
(I, B, M) +/–
(I, B, M) +/–
(M) +/–
(M) +/–
(I, B, M) +/–
(I, B, M) +/–
/OE –
(I, B, M) +/–
/OE +
t_OD2
Output Disable; from P-term⁴
t_PRO3
t_PPR3
Preset to Output
Power-on Reset (Mn = 1)
Hold Time
t_IH1
Input (Dedicated clock)
t_IH2
t_IH33
t_IH43
Input (P-term clock)
Input; from Mn (Dedicated clock)
Input; from Mn (P-term clock)
Pulse Width
t_CKH1
Clock High; Dedicated clock
t_CKL1
Clock Low; Dedicated clock
t_CKH2
Clock High; P-term clock
t_CKL2
Clock Low; P-term clock
t_PRH3
Width of preset/reset input pulse
Notes on page 80.
(I, B, M) +/–
(I, B, M) +/–
V_CC +
CK+
(I, B, M) +/–
CK+
(I, B, M) +/–
CK+
CK–
CK+
CK–
(I, B, M) +/–
TO
CK+
(I, B, M) +/–
CK+
(I, B, M) +/–
CK+
(I, B, M) +/–
(I, B, M) +/–
(I, B, M) +/–
(M) +/–
(M) +/–
(M) +/–
(M) +/–
(M) +/–
(M) +/–
(M) +/–
(M) +/–
(M) +/–
(B, M) +/–
Outputs dis-
abled
Outputs dis-
abled
(M) +/–
(M) +/–
(I, B, M) +/–
(I, B, M) +/–
(M) +/–
(M) +/–
CK–
CK+
CK–
CK+
(I, B, M) +/–
TEST²
CONDITION
(C_L (pF))
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
5
5
50
50
50
50
50
50
50
50
50
50
50
PLC42VA12
MIN TYP¹ MAX
23
16
20
13
10
3.5
2
–1.0
50
34
40
30
20
35
36
55
13
17
18
27
29
40
31
47
16.5 27
17
29
47
67
48
67
10
20
12.5 25
10
20
14.5 25
25
35
15
0
–13
5
–7.5
5
–1.5
10
3.5
10
5
10
5
15
7
15
7
30
7
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
October 22, 1993
79