BUK112-50GL Datasheet, PDF (9/16 Pages) NXP Semiconductors – PowerMOS transistor Logic level TOPFET

Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK112-50GL
a
1.5
Normalised RDS(ON) = f(Tj)
1.0
0.5
0
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
Fig.12. Normalised drain-source on-state resistance.
a = R_DS(ON)/R_DS(ON)25˚C = f(T_j); I_D = 6 A; V_IS ≥ 4.4 V
ID / A
50
BUK112-50GL
40
VPS = 0 V
30
20
VPS = 5 V
10
0
0
1
2
3
4
5
6
7
8
VIS / V
Fig.13. Typical transfer characteristics, T_j = 25˚C.
I_D = f(V_IS) ; conditions: V_DS = 10 V; t_p = 250 µs
ID / A
30
25
20
15
10
BUK112-50GL
VIS / V =
7
6
5
4.4
4
5
VPSP MIN.
0
4
5
6
7
8
VPS / V
Fig.14. Typical output current limiting, T_j = 25˚C.
I_D = f(V_PS); t_p = 250 µs; V_DS = 10 V; parameter V_IS
1 / [td sc / ms]
5
RECIPROCAL TRIP TIME
4
BUK112-50GL
3
intercept = PD(TO)
2
1/slope = EDSC
1
OVERLOAD DISSIPATION
0
0
200
400
600
800
1000
1200
PD / W
Fig.15. Typical reciprocal overload trip time.
1/t_{d sc} = f(P_D); conditions: V_PS = 5 V, T_mb = 25˚C
ESC(TO) / mJ
500
BUK112-50GL
400
300
TYP.
200
100
0
0
50
100
150
200
Tmb / C
Fig.16. Typical overload protection energy.
E_SC(TO) = f(T_mb); V_DD = 13 V; V_PS = 5 V, V_IS = 5 V
Tj(TO) / C
210
BUK112-50GL
200
190
TYP.
180
170
160
VPSP MIN.
150
3
Fig.17.
4
5
6
7
8
VPS / V
Typical overtemperature protection threshold.
T_j(TO) = f(V_PS); V_IS = 5 V; I_D ≥ 1 A
September 1996
9
Rev 1.000